CS35101 Computer Architecture Spring 2006 Week 2

Head’s Up  This week’s material l Introduction to MIPS assembler -Reading assignment - PH 2.1 through 2.7, omit 2.6  Reminders  Next week’s material l MIPS control flow operations -Reading assignment - PH 2.6

Review: Execute Cycle Processor Control Datapath Memory Devices Input Output contents Reg #4 ADD contents Reg #2 results put in Reg #2 The datapath executes the instructions as directed by control Memory stores both instructions and data

Review: Processor Organization  Control needs to have the l Ability to input instructions from memory l Logic and means to control instruction sequencing l Logic and means to issue signals that control the way information flows between datapath components l Logic and means to control what operations the datapath’s functional units perform  Datapath needs to have the l Components - functional units (e.g., adder) and storage locations (e.g., register file) - needed to execute instructions l Components interconnected so that the instructions can be accomplished l Ability to load data from and store data to memory Fetch DecodeExec

For a given level of function, however, that system is best in which one can specify things with the most simplicity and straightforwardness. … Simplicity and straightforwardness proceed from conceptual integrity. … Ease of use, then, dictates unity of design, conceptual integrity. The Mythical Man-Month, Brooks, pg 44

Assembly Language Instructions  Language of the machine  More primitive than higher level languages e.g., no sophisticated control flow  Very restrictive e.g., MIPS arithmetic instructions  We’ll be working with the MIPS instruction set architecture l similar to other architectures developed since the 1980's l used by NEC, Nintendo, Silicon Graphics, Sony, … Design goals: maximize performance, minimize cost, reduce design time, minimize memory space (embedded systems), minimize power consumption (mobile systems)

RISC - Reduced Instruction Set Computer  RISC philosophy l fixed instruction lengths l load-store instruction sets l limited addressing modes l limited operations  MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq) Alpha, …  Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them

MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2  Those operands are contained in the datapath’s register file ( $t0, $s1,$s2 )  Operand order is fixed (destination first)

MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2  Those operands are contained in the datapath’s register file ( $t0, $s1,$s2 )  Operand order is fixed (destination first)

Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d

Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d sub$t0, $s1, $s2 add$s0, $t0, $s3

MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file l Holds thirty-two 32-bit registers -With two read ports and -One write port  Registers are l Faster than main memory l Easier for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack l Can hold variables so that -code density improves (since register are named with fewer bits than a memory location)  Register addresses are indicated by using $

MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file l Holds thirty-two 32-bit registers -With two read ports and -One write port  Registers are l Faster than main memory l Easier for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack l Can hold variables so that -code density improves (since register are named with fewer bits than a memory location)  Register addresses are indicated by using $ Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations

0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

Registers vs. Memory  Arithmetic instructions operands must be registers, — only thirty-two registers provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output

Registers vs. Memory  Arithmetic instructions operands must be registers, — only thirty-two registers provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output

Accessing Memory  MIPS has two basic data transfer instructions for accessing memory lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory (assume $s3 holds )  The data transfer instruction must specify l where in memory to read from (load) or write to (store) – memory address l where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register

Accessing Memory  MIPS has two basic data transfer instructions for accessing memory lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory (assume $s3 holds )  The data transfer instruction must specify l where in memory to read from (load) or write to (store) – memory address l where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register 28 32

 Memory is viewed as a large, single-dimension array, with an address  A memory address is an index into the array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data

 Memory is viewed as a large, single-dimension array, with an address  A memory address is an index into the array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data  2 30 words

MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's complement Floating Point

Byte Addresses  Since 8-bit bytes are so useful, most architectures address individual bytes in memory  Therefore, the memory address of a word must be a multiple of 4 (alignment restriction)  Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA  Little Endian:rightmost byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

Addressing Objects: Endianess and Alignment  Big Endian: leftmost byte is word address  Little Endian: rightmost byte is word address msblsb little endian big endian Alignment restriction: requires that objects fall on address that is multiple of their size Aligned Not Aligned

Addressing Objects: Endianess and Alignment  Big Endian: leftmost byte is word address  Little Endian:rightmost byte is word address msblsb little endian byte big endian byte 0 Alignment restriction: requires that objects fall on address that is multiple of their size Aligned Not Aligned

MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory DataWord Address $s3 holds 8

MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory DataWord Address $s3 holds 8 in location

Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s A[2] A[3]... A[1] A[0]

Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s A[2] A[3]... A[1] A[0] lw$t0, 8($s3) sub$t0, $t0, $s2 sw$t0, 32($s3)

Compiling with a Variable Array Index  Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i

Compiling with a Variable Array Index  Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i add$t1, $t1, $s4#addr of A[i] lw$t0, 0($t1) sub$s2, $t0, $s1

MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1

A time was probably coming when components would operate so quickly that the distance that signals had to travel would intimately affect the speed of most commercial computers. Then miniaturization and speed would become more nearly synonymous. The Soul of a New Machine, Kidder, pg. 160

Review: MIPS Organization Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) ALU byte address (big Endian)  Arithmetic instructions – to/from the register file  Load/store instructions - to/from memory

0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Review: Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

Review: Unsigned Binary Representation HexBinaryDecimal 0x … x … x … x … x … x … x … x … x … x …10019 … 0xFFFFFFFC1…1100 0xFFFFFFFD1…1101 0xFFFFFFFE1…1110 0xFFFFFFFF1… bit bit position bit weight

Review: Signed Binary Representation 2’sc binarydecimal = -( ) = -2 3 = 1010 complement all the bits 1011 and add a 1

 Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18  Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct

 Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18  Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct

MIPS Instruction Fields  op  rs  rt  rd  shamt  funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits

MIPS Instruction Fields  op  rs  rt  rd  shamt  funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field

 Consider the load-word and store-word instructions, l What would the regularity principle have us do? l New principle: Good design demands a compromise  Introduce a new type of instruction format l I-type for data transfer instructions l previous format was R-type for register  Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number

 Consider the load-word and store-word instructions, l What would the regularity principle have us do? l New principle: Good design demands a compromise  Introduce a new type of instruction format l I-type for data transfer instructions l previous format was R-type for register  Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number

Memory Address Location  Example: lw $t0, 24($s2) Memory dataword address (hex) 0x x x x c 0xf f f f f f f f $s2 0x x $s2 = Note that the offset can be positive or negative

Memory Address Location  Example: lw $t0, 24($s2) Memory dataword address (hex) 0x x x x c 0xf f f f f f f f $s2 0x x $s2 = Note that the offset can be positive or negative = 0x120040ac

 Example: sw $t0, 24($s2)  A 16-bit address means access is limited to memory locations within a region of  2 13 or 8,192 words (  2 15 or 32,768 bytes) of the address in the base register $s2 Machine Language - Store Instruction op rs rt 16 bit number

 Example: sw $t0, 24($s2)  A 16-bit address means access is limited to memory locations within a region of  2 13 or 8,192 words (  2 15 or 32,768 bytes) of the address in the base register $s2 Machine Language - Store Instruction op rs rt 16 bit number

Assembling Code  Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS object code for these three instructions

Assembling Code  Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS code for these three instructions 35 lw sw sub

Review: MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's complement Floating Point

Beyond Numbers  Most computers use 8-bit bytes to represent characters with the American Std Code for Info Interchange (ASCII)  So, we need instructions to move bytes around ASCIICharASCIICharASCIICharASCIICharASCIICharASCIIChar 133!49165A97a113q 234“50266B98b114r 335#51367C99c115s 4EOT36$52468D100d116t 537%53569E101e117u 6ACK38&54670F102f118v 739‘55771G103g119w 8bksp40(56872H104h120x 9tab41)57973I105i121y 10LF42*58:74J106j122z ;75K107k123{ 12FF44,60<76L108l124| 1547/63?79O111o127DEL

Loading and Storing Bytes  MIPS provides special instructions to move bytes lb$t0, 1($s3) #load byte from memory sb$t0, 6($s3) #store byte to memory  What 8 bits get loaded and stored? l load byte places the byte from memory in the rightmost 8 bits of the destination register -what happens to the other bits in the register? l store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory op rs rt 16 bit number

Example of Loading and Storing Bytes  Given following code sequence and memory state (contents are given in hexidecimal), what is the state of the memory after executing the code? add$s3, $zero, $zero lb$t0, 1($s3) sb$t0, 6($s3) Memory A 0 DataWord Address (Decimal) F F F F  What value is left in $t0?  What if the machine was little Endian?

Example of Loading and Storing Bytes  Given following code sequence and memory state (contents are given in hexidecimal), what is the state of the memory after executing the code? add$s3, $zero, $zero lb$t0, 1($s3) sb$t0, 6($s3) Memory A 0 DataWord Address (Decimal) F F F F  What value is left in $t0?  What if the machine was little Endian? $t0 = 0x mem(4) = 0xFFFF90FF mem(4) = 0xFF12FFFF $t0 = 0x

Review: MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1 load byte32lb $s1, 101($s2)$s1 = Memory($s2+101) store byte40sb $s1, 101($s2)Memory($s2+101) = $s1

Review: MIPS R3000 ISA  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special  3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO OPrs rt rdshamtfunct OPrs rt 16 bit number OP 26 bit jump target Registers R format I format 6 bits5 bits 6 bits