SCT Upgrade DAQ SCTDAQ/HSIO Status Bruce Gallop, Ashley Greenall, Bart Hommels, Peter Phillips, Matt Warren ATLAS Upgrade Week, DESY, April 2010.

Slides:



Advertisements
Similar presentations
Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DCS – Frontend Monitoring and Control.
Advertisements

1 iTOP Electronics Effort LYNN WOOD PACIFIC NORTHWEST NATIONAL LABORATORY JULY 17, 2013.
ODR Status 29 July 2008 Matt Warren Valeria Bartsch, Barry Green, Andrzej Miesijuk, Tao Wu.
DMX512 Programmable Theater Lighting Controller Jeff Sand and Kris Kopel Advisor: Dr. Don Schertz.
P09311: Interface for Multi-Purpose Driver/Data Acquisition System Adam Van FleetProject Leader, EE DAQ Hardware Development David HoweElectrical Engineer.
Target Controller Electronics Upgrade Status P. Smith J. Leaver.
2 May 2013 Juergen Thomas: ATLAS Tracker Upgrade Module Chip-Bonding and Test Setup 1 ATLAS Tracker Upgrade: Hybrid Wire-Bonding and Test Setup at Birmingham.
12/09/2015Sheffield University 1 Target Electronics Recap - Decision has been made to rebuild the target electronics control system so that it is upgraded.
1 Fluke DAQ Software Visual Demo Guide 2680A-APSW.
Tuesday September Cambridge1 GDCC “next replacement of the LDA” Franck GASTALDI.
Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev AGATA PROJECT PREPROCESSING MEZZANINE SLOW CONTROL GUI FOR THE SEGMENT AND THE CORE.
Rome 4 Sep 04. Status of the Readout Electronics for the HMPID ALICE Jose C. DA SILVA ALICE.
Andy Blue Glasgow Update. Andy Blue WP3 Meeting Summary ESD Protection –Part all arrived and installed Compressed Air Controls –New lines and panel being.
Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Project Plan 2003 FED Project aiming to satisfy 2 demands/timescales: Module.
Edward Freeman CCLRC ESDG Optical Data Acquisition Development EID forum 12th October 2005 By Edward Freeman.
6th Feb 2003SCT DAQ analysis development 1 SCT analysis framework Work by:Alan Barr, Matt Palmer, Dave Robinson Almost all slides originally produced by.
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4 Marlon Barbero, Bonn.
Bart Hommels (for Matthew Wing) EUDET ext. steering board JRA3 DAQ System DAQ System Availability updates: – DIF: Detector Interface – LDA:
Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.
JRA-1 Meeting, Jan 25th 2007 A. Cotta Ramusino, INFN Ferrara 1 EUDRB: A VME-64x based DAQ card for MAPS sensors. STATUS REPORT.
1 Test Setups for the FE-I4 Integrated Circuit Stewart Koppell 8/1/2010.
SIDE SCAN HARDWARE CONFIGURATION
October Test Beam DAQ. Framework sketch Only DAQs subprograms works during spills Each subprogram produces an output each spill Each dependant subprogram.
Peter W Phillips Ashley Greenall Matt Warren Bruce Gallop 08/02/2013.
1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 6 Report Wednesday 6 th August 2008 Jack Hickish.
11 th April 2003L1 DCT Upgrade FDR – TSF SessionMarc Kelly University Of Bristol On behalf of the TSF team Firmware and Testing on the TSF Upgrade Marc.
SIDE SCAN HARDWARE CONFIGURATION HYPACK Connection Block Diagram GPS, single beam and tide data go into HYPACK ® SURVEY. Sidescan (with optional.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
Software and TDAQ Peter Lichard, Vito Palladino NA62 Collaboration Meeting, Sept Ferrara.
DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.
The Data Handling Hybrid Igor Konorov TUM Physics Department E18.
Scalable Readout System Data Acquisition using LabVIEW Riccardo de Asmundis INFN Napoli [Certified LabVIEW Developer]
András László KFKI Research Institute for Particle and Nuclear Physics New Read-out System of the NA61 Experiment at CERN SPS Zimányi Winter School ‑ 25.
Testing Setup Top dark box : Avalanche LED driver, 100ps pulse jitter, Fast response LED Triggering from generator Optical Fibre Bottom Box MCP, TORCH.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
E. Hazen1 MicroTCA for HCAL and CMS Review / Status E. Hazen - Boston University for the CMS Collaboration.
E. Hazen -- HCAL Upgrade Workshop1 MicroTCA Common Platform For CMS Working Group E. Hazen - Boston University for the CMS Collaboration.
Team Members: ECE- Wes Williams, Will Steiden, Josh Howard, Alan Jimenez Sponsor: Brad Luyster Honeywell Network Traffic Generator.
Configuration and local monitoring
The Data Handling Hybrid
DAQ and TTC Integration For MicroTCA in CMS
ATLAS Pre-Production ROD Status SCT Version
The STAR Heavy Flavor Tracker PXL detector readout electronics
Novosibirsk, September, 2017
Data and Control link via GbE
Vinculum II Development Modules
Status of the ODR and System Integration 31 March 2009 Matt Warren Valeria Bartsch, Veronique Boisvert, Maurice Goodrick, Barry Green, Bart Hommels,
E. Hazen - Back-End Report
ABC130: DAQ Hardware Status Matt Warren et al. Valencia 3 Feb 2014
Production Firmware - status Components TOTFED - status
The Data Handling Hybrid
ATF/ATF2 Control System
DAQ for ATLAS SCT macro-assembly
Experience with DAQ for ATLAS SCT
The DZero DAQ System Sean Mattingly Gennady Briskin Michael Clements
FrontEnd LInk eXchange
Online Software Status
MicroTCA Common Platform For CMS Working Group
Next steps – with notes from during the meeting 17 March 2016
Next steps - with notes from during the meeting 24 March 2016
Front-end digital Status
Hardware platforms - with notes from during the meeting 17 March 2016
The charge Define the DAQ for read-out and control of the CMOS submissions Identify the required resources for the CMOS specific developments including.
Front-end electronic system for large area photomultipliers readout
New Crate Controller Development
UK ECAL Hardware Status
NA61 - Single Computer DAQ !
Status of GbE Peripheral Crate Controller
State of developments on Readout interface of European DHCAL
Presentation transcript:

SCT Upgrade DAQ SCTDAQ/HSIO Status Bruce Gallop, Ashley Greenall, Bart Hommels, Peter Phillips, Matt Warren ATLAS Upgrade Week, DESY, April 2010

2 Apr 2010SCT DAQ - HSIO Firmware Update HSIO Hybrid (on panel) Interface Board 2 DAQ PC: SLC5 Intel PRO/1000 Fibre and Copper NICs Patch Board Fibre Network Interface (to DAQ PC) LVDS Interface (to Hybrid) USB and Copper Network Interface (to DAQ PC) Serial Powering Test System Setup (as at UCL)

3 Apr 2010SCT DAQ - HSIO Firmware Update Firmware Structure DAQ connection abstracted via common interfaceDAQ connection abstracted via common interface Each data-stream has dedicated deserialiser/FIFO logic blockEach data-stream has dedicated deserialiser/FIFO logic block – 1 per column of ABCNs –Organised in pairs to facilitate BCC/MCC multiplexed streams 16 streams muxed onto a single DAQ stream16 streams muxed onto a single DAQ stream –Uses plenty of flow control COM streams are formed in software and serialisedCOM streams are formed in software and serialised No stream decoding on HSIO (yet)No stream decoding on HSIO (yet) Data Stream Pair DAQ Interface Block Fiber Copper USB Common Packet Decoder Common Packet Formatter Register Block MUX/ Arbiter CLK_readout Data Stream Pair Deserialser/Header- Trailer Detect/FIFO x8 x16 reg_enables reg_mode ABCx_COM Interface_select ABCN/ Hybrid/ Module Interface LVDS RX LVDS TX Serialiser

4 Apr 2010SCT DAQ - HSIO Firmware Update Firmware Update Development is active, many improvements –Coupled closely to software development Multi-stream readoutMulti-stream readout –Handles 16 streams of ABCN data (i.e. 8x BCC) –Proper flow control –Scalable DAQ ConnectivityDAQ Connectivity –Fibre Ethernet –Copper Ethernet (up to 100Mb, likely 1Gb with new HSIO) –USB soon DAQ controlDAQ control –Writable registers – controls modes/readout clocks etc.

5 Apr 2010SCT DAQ - HSIO Firmware Update In progress USB Firmware is written, but untested on HSIOUSB Firmware is written, but untested on HSIO Full blown histogrammer systemFull blown histogrammer system –LBNL Module has been integrated, but untested Works on HSIO for ABCD, but not with SCTDAQ firmwareWorks on HSIO for ABCD, but not with SCTDAQ firmware Improved packet handlingImproved packet handling –Simulate more realistic “asynchronous” conditions –Add multiple packets for long events capability I2C MonitoringI2C Monitoring –Started at LNBL –Needs dedicated data-streams on HSIO and control logic User selectable header/trailer, raw stream captureUser selectable header/trailer, raw stream capture –For BCC ID/register readback - has no header Jumper selectable DAQ interface – Fibre/Copper/USBJumper selectable DAQ interface – Fibre/Copper/USB

6 Apr 2010SCT DAQ - HSIO Firmware Update Next steps Individual delays on all input streamsIndividual delays on all input streams Register readbackRegister readback –Currently we can only look at the display! Add more status registersAdd more status registers –Trigger/header counters Implement other types of control and readbackImplement other types of control and readback –Blocks –FIFOs –Autonomous status reports Full Histogrammer sub-systemFull Histogrammer sub-system –Assess best structure – 1 per channel or shared? Scale to 48 channelsScale to 48 channels –May need effort on logic reduction to fit FPGA –Coupled to histogrammer config

7 Apr 2010SCT DAQ - HSIO Firmware Update SCT Upgrade DAQ HSIO Software Status

8 Apr 2010SCT DAQ - HSIO Firmware Update Evolution, not Revolution! 1.Modify SCTDAQ to readout ABCN-25 and BCC using MuSTARD/SLOG VME modulesusing MuSTARD/SLOG VME modules 2.Modify SCTDAQ to support other hardware principle demonstrated with NI-6562 card used for wafer screeningprinciple demonstrated with NI-6562 card used for wafer screening 3.Modify SCTDAQ for basic HSIO support send Ethernet packets to HSIOsend Ethernet packets to HSIO configuration registersconfiguration registers prepared command streams for ABCN-25 hybridsprepared command streams for ABCN-25 hybrids receive Ethernet packets from HSIOreceive Ethernet packets from HSIO decode and histogram ABCN-25 eventsdecode and histogram ABCN-25 events 4.Support additional firmware features as they become available USBUSB histogramming and scan controlhistogramming and scan control register readbackregister readback end of stave DCS (temperature readout and 1-wire control)end of stave DCS (temperature readout and 1-wire control) Present Future

9 Apr 2010SCT DAQ - HSIO Firmware Update Platforms and Interfaces SLC5SLC5 Custom driver for raw ethernet packetsCustom driver for raw ethernet packets –Bruce –Copper at 10 Mbps –Copper at 100 Mbps –Fibre at 1Gbps Windows XP or 7 Interface to WinPCAP raw packet driver –Peter –Copper at 10Mbps –Copper at 100Mbps –Fibre untested no fibre NIC in my laptop!

10 Apr 2010SCT DAQ - HSIO Firmware Update SCTDAQ Stavelet GUI Features: Menu bar Dialog boxes to set parameters Tabbed display shows data for 4 modules

11 Apr 2010SCT DAQ - HSIO Firmware Update But does it work? This preliminary plot shows a raw data burst for one ABCN-25/BCC module. We have recorded analogue test data from a single hybrid, but not yet from a module. To be continued…