University of Michigan Advanced Computer Architecture Lab. 2 CAD Tools for Variation Tolerance David Blaauw and Kaviraj Chopra University of Michigan

-3- Variability Tolerant CAD Re-Tooling Goal: Make designs tolerant to process variation Variation tolerant CAD Tools Statistical Analysis Statistical Optimization

-4- Research in SSTA SSTA paper count in DAC Major focus on addition and max function in arrival time propagation A MAX SUM

-5- Current Functionality of STA STA development since 1982 PERT analysis Slope / Delay Modeling False Path Analysis Transparent Latches Clocking Signal Pruning Interconnect Modeling Multiple Input Switching

-6- Challenges for SSTA Modeling data for SSTA Which process parameters are most critical to model ?  L eff, V th, T ox, doping, ILD thickness, metal thickness, metal width. Tracking process as it matures Obtaining inter-die Variation, Intra-die Variation and spatial information from raw data. Representing variation in the cell library P L eff Across wafers btween die Within die

-7- Introduction Statistical Performance Analysis Tools Early Timing Estimation, floor planning, synthesis Sign off Timing Post Synthesis Optimization Sizing, Buffer insertion, Vt assignment, etc Credibility ? Discrepancies? Deterministic Statistical Timing Toolbox Process Uncertainty Analysis Uncertainty > Initial Adoption? Early Timing Estimation, floor planning, synthesis Sign off Timing Post Synthesis Optimization Sizing, Buffer insertion, Vt assignment, etc

-8- Conventional Deterministic Timing Optimization Path Delay Distribution #Paths t max delay Pre-Optimization T max Distribution T max 99 T max P  T max 99 <  t max #Paths t max delay Post-Optimization  t max t max T max 99 T max P  t max

-9- #Paths t max Impact of recovering power through sizing, restructuring,… Low Power Optimization Uncertainty T max P delay Pre Optimization T max 99 Post Dynamic Voltage Scaling Lower voltage operation increases sensitivity to V th variation. Clock gating & Power gating (MTCMOS) Variability in arrival time of control signals

-10- Low Power Optimization Uncertainty For a single transistor: ±10% in Ld  300% in leakage For a full chip: 20X variation in total leakage ±10% L d ±100% I sub High Frequency High Leakage Low Leakage Low frequency Borkar ‘02

-11- Optimization objective Joint power delay probability distribution Maintains correlations between power and delay Allows computation of yield P const T const

-12- Conclusion Significant research still needed for complete SSTA solution Key challenge in obtaining data for SSTA Annotating library information Track process Find most likely adoption point for statistical solutions Opportunity in statistical optimization for yield enhancement Must model both leakage and delay