Project characterization Encryption/Decryption on embedded system Supervisor: Ina Rivkin students: Chen Ponchek Liel Shoshan Winter semester 2014 Part A

motivation Now days, there are many portable storage systems with large memories which contains valuable data (such as disk on key, tablets, etc.) Therefore there is a concrete need for portable cryptography systems which are suitable for such devices. In our project, we will aspire to provide a suitable system which will answer this need.

Project Goal main goal: Implementation of data cryptography embedded system using AES algorithm and finding the suitable architecture for portable system.

Project Specifications Implementing on a Zync SoPC by Xilinx. Suitable for portable systems (Disk-on-Key, tablets, etc.) - low power system. Transparent system (while storing/loading files) - The cryptography system wouldn’t create traffic bottle necks. Finding the best architecture – according to the requirements above: Profiling AES algorithm. Finding the balance between using the ARM processor and using the FPGA (the hardware accelerator needs more power).

AES algorithm Advanced Encryption Standard, also known as “Rijndael”, is a block cipher, which has been adopted at November 2001 by NIST (National Institute of Standard and Technology), as standard FIPS PUB 197. The algorithm was developed by two Belgian cryptography experts Joan Daemen and Vincent Rijmen. The cipher is iterative, quick and comfortable to implement both by software and hardware, and it doesn’t have high memory requirements.

Algorithm Description Most of the AES calculations are made through 10 rounds. In each state the data block is described as a 2D, 4X4 array of bytes. In each round a “Round Key” is created by the key-expansion process. Each round consists of 4 steps: 1.SubBytes 2.ShiftRows 3.MixColumns 4.AddRoundKey

Algorithm Steps 1.SubBytes Non linear interchange process of the state bytes, made separately on each byte, using the static switch table (S-box). The decryption process uses the inverse table.

2.ShiftRows Cyclic Shift process in which the rows of the state are shifted by different offsets, according to some constant values. (The first row is left unchanged.) Algorithm Steps

3.MixColumns Linear transformation process, where each state column is treated as a polynomial over GF(2 8 ) and is then multiplied modulo x 4 +1 with a fixed polynomial c(x) = 3x 3 + x 2 + x +2. Algorithm Steps

4.AddRoundKey RoundKey which is created by Key Expansion Process and fits the dimensions of the state, XOR-ed with all the state bits. Algorithm Steps

Result After a few rounds, according to the key size, an encrypted block is generated. The decryption process is includs the same 4 steps, and the operations are inverse. Example: For the following Input data and cipher key The encryption process will look like this:

AddRoundKeySubBytesShiftRowsMixColumnsAddRoundKey SubBytesShiftRowsAddRoundKey Inv ShiftRows Inv SubBytes AddRoundKey Inv MixColumns Inv ShiftRows Inv SubBytes AddRoundKey Key Expansion data encrypted data encrypted data xNR key Cipher Inverse Cipher

PS UART DDR System Block diagram RS232 PL ZEDBOARD Encrypted data Decrypted data Zynq

PS UART Out Memory In Memory RS232 PL ZEDBOARD Encrypted data Decrypted data Zynq System Block Diagram

Zedboard Block Diagram

PS UART Out Memory In Memory RS232 PL ZEDBOARD Encrypted data Decrypted data Zynq AES in software System Block Diagram project part A Implementation of AES algorithm on ARM and code optimization.

PS UART Out Memory In Memory RS232 PL ZEDBOARD Encrypted data Decrypted data Zynq Profiling of AES algorithm- finding the best architecture. Implementation of embedded encryption system using the AES algorithm (on ARM and accelerator on programmable logic). AES in hardware AES in software System Block Diagram project part B

Tools and development environment PlanAhead- hardware design (VHDL), simulation and synthesis tool. XPS/EDK- configuring the embedded system. SDK - software development kit. Visual Studio. ZedBoard - including Zynq SOPC.

Project Time-table הכרת אלגוריתם AES – לימוד הפרוטוקול והרצה על PC. למידת הכלים (PlanAhead, SDK, EDK ). יצירת מתי מצגת אמצע מטרות למצגת אמצע : למידת הכלים + הדפסת תוכנית בסיסית "HELLO WORLD". Learning the tools - PlanAhead, SDK, EDK. Creating a simple embedded system (“hello world”). Learning the AES algorithm – learning the protokol, run on PC. מצגת אמצע

MixColumns() Transformation