® XC9500XL CPLDs Technical Presentation

® XC9500XL Overview  Superset of XC9500 CPLD  Optimized for 3.3V systems —compatible levels with 5.0/2.5V  High f MAX = 200 MHz  Fast t PD = 4 nsec  Best ISP/JTAG support  Best pin-locking  Advanced packaging

® Agenda  Overview  Technology  Architecture  Timing  ISP  Electrical Compatibility  Support  Family

® XC9500XL Features  Each macrocell independently selects clock source and phase inversion  Clock enable at each macrocell  Hysteresis on all inputs  Pull-up/bus-hold option on pins at power on  Extra-wide function block inputs

® Technology  Optimized for high speed 3.3V systems  Leading-edge FLASH technology —0.35um feature-size (0.25um Leff) —4 layers of metal  Superior reliability —Reprogramming endurance = 10,000 —Charge retention = 20 years  Fast programming characteristics

® Flash vs E 2 Endurance Relative Endurance (#programming cycles) AlteraXilinx Vendor Reprogramming Cycles  Flash delivers: — Highest quality — No speed degradation — 20 year retention — Reliable reprogramming — Worry free field upgrade

® XC9500XL Architecture  Uniform architecture  Identical function blocks  Identical macrocells  Identical I/O pins  Abundant global/product term resources  Optimized synthesis results  Superior pin-locking characteristics

® High Level Architecture

® FastCONNECT II Switch Matrix  Very high speed switch matrix  Greater connectability for all signals  High routability at high utilization  Software delivers high speed automatically  Substantial power reduction

® XC9500XL Function Block  54 Inputs  Highest FB Fanin

® XC9500XL Macrocell

® Cascading 2 p-terms required here 5 available here 5 native p-terms 3 available here Total = 18 requires 2 cascade times added to t PD

® Timing

® Timing Example 1 Function Block t IN t OUT t PDI + t LOGI t PD = t IN + t PDI + t LOGI + t OUT

® Timing Example 2 B Function Block t IN t OUT t LOGI + t PDI t PTA t A-> B = t IN + t PTA + t LOGI + t PDI + t OUT A

® Timing Example 3 D/T Q GCK t GCK t HI t SUI t SU = t IN + t LOGI + t SUI - t GCK t CO = t GCK + t COI + t OUT t H = t GCK + t HI - t IN - t LOGI

® ISP  Original XC9500 JTAG and ISP instructions  New instruction: CLAMP —Permits pin by pin definition of logic level  Added S/W support Foundation & WebPACK  Same third party and ATE support package as XC9500 CPLDs (HP, GenRAD, Teradyne)

® Voltage Compatibility CORE LOGIC V CCINT = 3.3V V CCIO = 3.3V/2.5V Note: output p-channel gives full rail swing

® Voltage Compatibility 3.3V/5V 5V 3.3V Any 5V TTL device XC9500XL Any 3.3V device V CCIO V CCINT 5V 3.3V

® Voltage Compatibility 3.3V/2.5V 3.3V 2.5V Any 3.3V device XC9500XL Any 2.5V device VCCIOVCCINT 3.3V 2.5V

®  EIA Standard Voltage Levels  No Power Supply Sequencing Restriction XC9500XL Voltage Compatibility Summary

® Input Signal Hysteresis V OH V OL 1.40V 1.45V V OUT V IN (VOLTS) 50 mV

® Power Optimization  67% decrease from 5V CPLDs  Low power option per macrocell  Even lower power if I/Os swing 0-2.5V  FastCONNECT II lower power than XC9500  I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)

® XC9500XL Design Software  XC9500XL Fitters in all Xilinx Standard S/W Packages —Foundation —Alliance  Support for Schematics, Verilog, VHDL, Abel —Exemplar —Synopsys —Synplicity —More

® Third Party ATE Support  Hewlett-Packard  Teradyne  Gen-RAD  Common Support for both Xilinx FPGAs and CPLDs

® XC9500XL Family 9536XL9572XL95144XL95288XL Macrocells Usable Gates t PD (ns) f MAX (MHz) Packages QFP CSP/BGA 44PC 64VQ 48CS 44PC 64VQ 100TQ 48CS 100TQ 144TQ 144CS 144TQ 208PQ 352BG

® The Next Generation CPLD  Leadership speed - 4ns/200MHz  Powerful new architecture  Highest programming reliability  FastFLASH technology