- LHCb calorimeter upgrade April 15th, 2011 1 News and ideas on DAQ architecture Frédéric Machefert LAL, Orsay.

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Presentation transcript:

- LHCb calorimeter upgrade April 15th, News and ideas on DAQ architecture Frédéric Machefert LAL, Orsay

- LHCb calorimeter upgrade April 15th, News Letter Od Intent was presented to the LHCC Very well received Physics case considered as excellent Flavour physics case with 50fb -1 compelling Upgrade extends the physics reach Other domain than Flavour physics also benefit from upgrade Quick progress requested Next step is the TDR Funding will become an issue Need to as approval from the institutes (example IN2P3 in France) soon New person in charge of the Upgrade from May 1 st Andreas The role of the upgrade working group was to write the LOI → done ! Could expect the persons in charge change and the duty of the group is redefined

- LHCb calorimeter upgrade April 15th, Power supplies This was the subject of the meeting of yesterday Have a look at the DCDC converter presentation from CERN group The main issue is the usage of DCDC converters/linear regulators According to me, the picture is not clear on what we should do for the front-end Can we use DCDC converter Tests should be done with samples provided Noise Input/output voltage ranges It seems that 7V input voltage is fine 1.5V output seems also ok → moreover, the requirement of many customers ! But, can we directly power some electronics part with Maraton (backplane) At present, this is the case for the PRS/ECAL/HCAL ADC This did not have bad side effect Noise is perfectly fine Could we do a test to measure the effect of power supply noise on the front- end?

- LHCb calorimeter upgrade April 15th, ECAL – Front-end Architecture 96 boards on each side Includes 2 pin-diode FEB for monitoring A FEB is 32 channels 4 optical link GBT

- LHCb calorimeter upgrade April 15th, HCAL – Front-end Architecture 27 boards on each side Includes 2 pin-diode FEB for monitoring A FEB is 32 channels 4 optical link GBT

- LHCb calorimeter upgrade April 15th, DAQ : preliminary idea ECAL (total of 8 ATCA – 8x4 AMC) 96 FEB per side 4 link per FEB 4 ATCAper side 3 mezzanines AMC/ATCA 6 FEB per mezzanine Total of 4 ATCA/side Optimisation vs crate splitting HCAL (total of 3 ATCA – 4+2x3 AMC) 27 boards per side (incl. 4 pin-diode) Read full inner in 1 ATCA board 2 crates for 2 sides 11(1 crate)+11=22 FEB inner 2(2) AMC for side C/(A) Read outer (2x14 FEB) in 2 ATCA 4 Pin-diode read out with outer Pin-diode side correspond to outer ATCA side

- LHCb calorimeter upgrade April 15th, Clock-Slow control-Commands A new board plugged in central slot of the ECAL/HCAL crates Receives Clock Slow control Commands Propagates signals to the FEB ~CROC without DAQ, debugging (7+2)+(7+2) = 18 crates → 2 ECS mezz. ECAL/HCAL integrators SPECS mezza → GBT mezzanines 2+4 are needed → 1 ECS mezz. In FEB ECS40 ECAL/HCAL HV_DAC boards GBT mezzanines 32+8 → 3+1 ECS mezz. Calibration source CAN Bus → keep it

- LHCb calorimeter upgrade April 15th, ECAL 8 ATCA 4 for side A (max load → 4x4 mezz.) 4 for side C (max load → 4x4 mezz.) HCAL 3 ATCA 1 for inner (both sides in same ATCA, 2 mezz. per side) 2 for outer (A and C splitting) and pin-diodes (also split in A and C Sides) ECS is 2 ATCA 1 for FEB + Integrator readout (3 mezz) 1 for HV control (3+1 mezz. For ECAL and HCAL respectively) Is the ECS (PVSS) load acceptable for a single ECS40 ? Had to split the calo ECS to have an acceptable response in current design 13 ATCA in total Maximum number of slots in an ATCA crate is required → prefer to have an experiment dedicated ECS crate ! Overall Achitecture