© 2003-2008 BYU LC3-3 Page 1 ECEn 224 The LC-3 State Machine.

Slides:



Advertisements
Similar presentations
The CPU The Central Presentation Unit What is the CPU?
Advertisements

Fetch-Execute cycle. Memory Read operation Read from memory.
The Fetch – Execute Cycle
Machine cycle.
Central Processing Unit
Control path Recall that the control path is the physical entity in a processor which: fetches instructions, fetches operands, decodes instructions, schedules.
Damian BrowneLuis PabonPedro Tovar The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Microprocessor.  The CPU of Microcomputer is called microprocessor.  It is a CPU on a single chip (microchip).  It is called brain or heart of the.
Lecture 13 - Introduction to the Central Processing Unit (CPU)
Computer Science 210 Computer Organization The Instruction Execution Cycle.
The von Neumann Model – Chapter 4 COMP 2620 Dr. James Money COMP
Review for Exam 3 LC3 control State Graphs
Computer Science 210 Computer Organization The von Neumann Architecture.
1 Computer Organization Today: First Hour: Computer Organization –Section 11.3 of Katz’s Textbook –In-class Activity #1 Second Hour: Test Review.
Computer Architecture and the Fetch-Execute Cycle
Computer Architecture and the Fetch-Execute Cycle
EXECUTION OF COMPLETE INSTRUCTION
CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.
Computer Architecture Lecture 09 Fasih ur Rehman.
The von Neumann Model – Chapter 4
Model Computer CPU Arithmetic Logic Unit Control Unit Memory Unit
Review for Final Exam LC3 – Controller FPGAs Multipliers
Fetch-execute cycle.
TEAM FRONT END ECEN 4243 Digital Computer Design.
COMPILERS CLASS 22/7,23/7. Introduction Compiler: A Compiler is a program that can read a program in one language (Source) and translate it into an equivalent.
The von Neumann Model – Chapter 4 COMP 2620 Dr. James Money COMP
© BYU LC3-DC Page 1 ECEn 224 LC3-DC Designing The LC-3 Control IR PC enaMARMenaPC enaALU enaMDR ALU AB.
09 MUX Page 1 ECEn/CS 224 Multiplexers Decoders ROMs (LUTs)
Processor Organization and Architecture Module III.
Designing a CPU –Reading a programs instruction from memory –Decoding the instruction –Executing the instruction –Transferring Data to/From memory / IO.
Chapter 20 Computer Operations Computer Studies Today Chapter 20.
Lec 4-2 Five operations of the machine cycle Fetch- fetch the next program instruction from memory. (PC+1); instruction to IR Decode- decode the instruction.
LC-3 Datapath ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin – Madison.
SAP1 (Simple-As-Possible) Computer
ECE 4110–5110 Digital System Design
Lecture 13 - Introduction to the Central Processing Unit (CPU)
Gunjeet Kaur Dronacharya Group of institutions
Computer Science 210 Computer Organization
Chapter 4 The Von Neumann Model
Five Execution Steps Instruction Fetch
ADVANCED PROCESSOR ARCHITECTURE
Chapter 4 The Von Neumann Model
Computer Science 210 Computer Organization
The Processor and Machine Language
Chapter 4 The Von Neumann Model
Computer Science 210 Computer Organization
Computer Science 210 Computer Organization
Functional Units.
Topic 6 LC-3.
The Little Man Computer
von Neumann Architecture CPU
Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations.
THE FETCH-EXECUTE CYCLE.
Joseph Ravichandran, Srijan Chakraborty, Kanad Sarkar
Chapter 4 The Von Neumann Model
Multicycle Design.
KU College of Engineering Elec 204: Digital Systems Design
The Stored Program Computer
Program Execution.
Basic components Instruction processing
THE FETCH-EXECUTE CYCLE.
A Top-Level View Of Computer Function And Interconnection
Objectives Describe common CPU components and their function: ALU Arithmetic Logic Unit), CU (Control Unit), Cache Explain the function of the CPU as.
Instruction execution and ALU
Computer Architecture
Arithmatic Logic Unit (ALU). ALU Input Data :  A0-A3  B0-B3 Output Data :  F0 – F3.
Instruction Set Architecture
Presentation transcript:

© BYU LC3-3 Page 1 ECEn 224 The LC-3 State Machine

© BYU LC3-3 Page 2 ECEn 224 Output Forming Logic Current State Input Forming Logic FF LC-3 Datapath FF.....

© BYU LC3-3 Page 3 ECEn 224 OFLIFL LC-3 Datapath Next State Current State Datapath Control Datapath Status FF.....

© BYU LC3-3 Page 4 ECEn 224 Instruction Fetch Example 1. Copy PC contents to MAR enaPC = 1 & ldMAR= 1 2. Perform memory read selMDR=1 & ldMDR=1 Increment PC selPC = 00 & ldPC = 1 3. Copy memory output register contents to IR enaMDR = 1 & ldIR = 1 IR PC ALU enaPC ldMAR ldPC selPC selMDR ldMDR enaMDR ldIR AB

© BYU LC3-3 Page 5 ECEn 224 CSNS fetch0fetch111xx0x000 fetch1fetch fetch2decode00xx0x011 decode???? ????? enaPC ldMAR selPC ldPC enaMDR ldIR Current State Next State Outputs Fetch Control Sequence selMDR ldMDR

© BYU LC3-3 Page 6 ECEn 224 The Control Logic Examples: IR[8:6] IR[2:0] IR[11:9] BranchTaken

© BYU LC3-3 Page 7 ECEn 224 The Control Logic IRNZP DR SR2selMARselPCaluControlSR1 ldMDRldMARregWEldPCldIR memWE enaMARMenaALUenaMDRenaPC selEAB1selEAB2selMDRflagWE IFL Flip Flops OFL