Research in ATI © Raimund Ubar 4. High-Level Decision Diagrams Overview and examples Register Transfer Level circuits Microprocessors Methods of synthesis Structural superposition of elementary graphs Synthesis with symbolic executions of Data Flow Diagrams Synthesis with with using the FSM model Fault modeling with HLDDs HLDD-node related general fault model for digitaal systems HLDD based fault collapsing 1

Research in ATI © Raimund Ubar 2 Simulation: Boolean derivative: y x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x Functional BDD Logic Level BDDs

Research in ATI © Raimund Ubar Generalization of BDDs m y 1 0 lmlm l1l1 l0l0 GyGy m Y h FkFk FnFn l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GYGY Binary DD 2 terminal nodes and 2 edges from each node General case of DD n  2 terminal nodes and n  2 edges from each node Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels 3

Research in ATI © Raimund Ubar HLDDs and Faults RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: (If T,C) R D  F(R S1,R S2,…R Sm ),  N 4 Control path Data path

Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Instruction set: IA 2 R IN 5 R 1,3,4,6-10 AIIN 1,6 IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 IR 3 A OUT 4 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

Research in ATI © Raimund Ubar 7 OPBSemanticRT level operations 0 0READ memoryR(A1) = M(A)PC = PC + 2 1WRITE memoryM(A) = R(A2)PC = PC TransferR(A1) = R(A2)PC = PC + 1 1Complement R(A1) =  R(A2) PC = PC AdditionR(A1) = R(A1)+ R(A2)PC = PC + 1 1SubtractionR(A1) = R(A1)- R(A2)PC = PC JumpPC = A 1Conditional jumpIF C=1, THEN PC = A,ELSE PC = PC + 2 From MP Instruction Set to HLDDs OP B 0 M(A) 1 R(A2) M(A) OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) Instruction code: ADD A1 A2 R 3 = R 3 + R 2 PC = PC+1 OP=2. B=0. A1=3. A2=2

Research in ATI © Raimund Ubar 8 HLDDs for MP InstrSet A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Registers and ALU A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 Register Decoding OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C Program Counter OP B 0 M(A) 1 R(A2) M(A) Memory Access Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

Technical University Tallinn, ESTONIA Structural Synthesis of HLDDs Data Path Control Path y x

Technical University Tallinn, ESTONIA Data Path: High-Level DD Synthesis Data Path Control Path y x y 4 e R  0 R 2

Technical University Tallinn, ESTONIA Structural Synthesis of HLDDs Data Path Control Path y x Superposition of component HLDDs 11 y 4 e R R 2 y 4 y 3 c d R  0 R 2 IN R R 2 R 2 +e y 3 c d 0 1 R e

Technical University Tallinn, ESTONIA Data Path: HLDD Synthesis Data Path Control Path y x y 4 y 3 c d R  0 R 2 IN R R2R2 R 2 + e

Technical University Tallinn, ESTONIA High-Level Decision Diagrams Superposition of High-Level DDs: A single DD for a subcircuit Instead of simulating all the components in the circuit, only a single path in the DD should be traced y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R  0 R 2 IN R R2R2 R 2 + M 3 M1M1 M2M2

Technical University Tallinn, ESTONIA Functional Synthesis of High-Level DDs Data-Flow Diagram High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram F2

Technical University Tallinn, ESTONIA Synthesis of High-Level DDs High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram: Decision Diagrams: F0AC AC+1 F1 AC AX F AX AC AX 0 F0 1 0 F PC PC+1 AC ≠0 F0 1 0 F PC

Research in ATI © Raimund Ubar 16 A B C M ADR MUX 1 2 ALU COND Control Path Data Path  / FF y x q q z z 1 z 2 Digital system Data Flow Diagram q=0 q=1 q=4 q=2 q=3 q=5 Digital System and Data Flow Diagram

Research in ATI © Raimund Ubar Synthesis of Functional HLDDs Data Flow Diagram/FSMD Begin A = B + C x A A =  A + 1 B = B + C x A B =  BC =  C x B  C x C A = A +  B + C x C C = A + B A =  C + B END Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = q = 5 41 C = C; q = 5 Results of cycle based symbolic simulation: q = 0 q = 1 q = 2 q = 3 q = 4 q = 5

Research in ATI © Raimund Ubar Synthesis of HLDDs Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = q = 5 41 C = C; q = 5 Results of symbolic simulation: qxAxA xBxB xCxC A 0B + C 10 A C + B 400 A + B + C Extraction of the behaviour for A: A = f (q, A, B, C, x A, x C ) = = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A:

Research in ATI © Raimund Ubar Synthesis of HLDDs qxAxA xBxB xCxC A 0B + C 10 A C + B 400 A + B + C Extraction of the behaviour for A: A = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A: Decision diagram for A: Synthesis method: similar to Shannon’s expansion theorem:

Research in ATI © Raimund Ubar Functional HLDDs Data Flow DiagramDecision Diagrams Register variables State variable

Research in ATI © Raimund Ubar 21 Managing Complexity of HL Reasoning A=F A1 (...) B=F B1 (...) C=F C1 (...) A=F A2 (B,C,...) A=F An (D,E,...) State space Program data flow Behavior of A D E B C High-Level Decision Diagrams Novelty: Instead of reasoning the design as a whole, it will be partitioned into the behavioral sub-models of functional variables (HLDDs)

Research in ATI © Raimund Ubar 22 System with 4 HLDDsVector HLDD High-Level Vector Decision Diagrams

Research in ATI © Raimund Ubar 23 System with 4 HLDDsVector HLDD High-Level Vector Decision Diagrams

Research in ATI © Raimund Ubar 24 M=A.B.C.q 1 1 q x A 0 q A i B’ + C’ #1 q B i #2 0 q A i  A’ + 1 #4 2 1 x B q C i  C’ #3 0 q C i A’ + B’ #5 3 1 x C q A i B’ +  C’ #5 0 q C i A’ + B’ #5 4 1 x C q C i  C’ #5 0 B A i x A 0 q  B’ q B i  #5 System: High-level decision diagram A small part is simulated at the higher level: to increase the speed of analysis Cause-effect analysis well formalized B’ + C’ Hierarchical Test Generation with DDs A’ + B’+C’ x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x C Component: Binary Decision Diagram A small part is simulated at the lower level

Research in ATI © Raimund Ubar DD Synthesis from VHDL Descriptions VHDL description of 4 processes which represent a simple control unit

Research in ATI © Raimund Ubar 26 DDs for state, enable_in and nstate nstate rst clk  #1 state’ state clk enable’ enable 1 enable_in 0 Synthesis of HLDDs from VHDL state’ rb0 enable_in #2 # nstate Superposition of DDs

Research in ATI © Raimund Ubar 27 Synthesis of HLDDs from VHDL enable #0011 # enable #0100 # state rb # outreg fin reg_cp reg rst #1 nstate 1 0 state’ rb0 enable' #2 # HLDD model for the Control Unit

Research in ATI © Raimund Ubar 28 Simulation & Fault Backtracing with HLDD rst #1 state 1 0 state’ rb0 enable' #2 # enable #0011 # enable #0100 # state rb # outreg fin reg_cp reg Simulated vector Inputs Outputs

Technical University Tallinn, ESTONIA 29 Motivations for High-Level Fault Models Current situation: The efficiency of test generation (quality, speed) is highly depending on –the description method (level, language), and –fault models Because of the growing complexity of systems, gate level methods have become obsolete High-Level methods for diagnostic modeling are today emerging, however they are not still mature Main disadvantages: The known methods for fault modeling are –dedicated to special classes (i.e. for microprocessors, for RTL, VHDL etc. languages...), not general –not well defined and formalized

Research in ATI © Raimund Ubar State of Art: Microprocessor Fault Model Source decoding (MUX): F1: no source is selected F2: wrong source is selected; F3: more than one source is selected and the multiplexer output is either a wired-AND or a wired-OR function of the sources, depending on the technology. Destination decoding (DMUX) F4: no destination is selected F5: instead of, or in addition to the selected correct destination, one or more other destinations selected Instruction exec. faults F6: one or more microorders not activated F7: microorders are erroneously activated F8: a different set of micro- instructions is activated instead of, or in addition to Data storage/bus/ALU faults: F9: one or more cells SAF0 /1; F10: one or more cells fail 01/10 F11: two or more cells coupled; F12: one or more lines SAF0 /1; F13:one or more lines wired-OR/AND F14: data manipulation faults Thatte’1980

Technical University Tallinn, ESTONIA 31 Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer ( n inputs log 2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

Technical University Tallinn, ESTONIA 32 Fault models and Tests Dedicated functional fault model for multiplexer: –stuck-at-0 (1) on inputs, –another input (instead of, additional) –value, followed by its complement –value, followed by its complement on a line whose address differs in one bit Functional fault model Test description

Technical University Tallinn, ESTONIA 33 Register Level Fault Models K: ( If T,C) R D  F(R S1, R S2, … R Sm ),  N RTL statement: K- label T- timing condition C- logical condition R D - destination register R S - source register F- operation (microoperation)  - data transfer  N- jump to the next statement Components (variables) of the statement: RT level faults: K  K’- label faults T  T’- timing faults C  C’- logical condition faults R D  R D - register decoding faults R S  R S - data storage faults F  F’- operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults

Technical University Tallinn, ESTONIA 34 Universal Functional Fault Model Exhaustive combinational fault model: - exhaustive test patterns - pseudoexhaustive test patterns - exhaustive output line oriented test patterns - exhaustive module oriented test patterns

Technical University Tallinn, ESTONIA 35 Hierarchical Test Generation & & & 1 & x1x1 x2x2 x4x4 x5x5 y x3x3 & & D D D1D1 D1D1 D2D2 D2D Component under test Component level test: D1D1 D2D2 D Network level test: x1x1 x2x2 x3x3 x4x4 x5x5 y D2D2 0 D1D1 11D Symbolic test: contains 3 patterns

Research in ATI © Raimund Ubar HLDDs and Faults RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: (If T,C) R D  F(R S1,R S2,…R Sm ),  N 36 Control path Data path

Research in ATI © Raimund Ubar Generalization of BDDs m y 1 0 lmlm l1l1 l0l0 GyGy m Y h FkFk FnFn l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GYGY Binary DD 2 terminal nodes and 2 edges from each node General case of DD n  2 terminal nodes and n  2 edges from each node Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels 37

Research in ATI © Raimund Ubar From Trad. MP Fault Model to HLDD Faults D1: node output is always activated (SAF-1) D2: node output is broken (SAF-0) D3: instead of the given output another output set is activated Instead of the 14 fault classes,the HLDD based fault model includes only 3 fault classes Each path in a DD represents a working mode of the system The faults having effect on the behaviour can be associated with nodes along the path

Research in ATI © Raimund Ubar Each node in SSBDD represents a signal path: Two SSBDD faults x 11 1, x 11 0 represent a set of six faults in the circuit: {x 11 1, x 6 1, y1; x 11 0, x 6 0, y0} Fault Collapsing with SSBDDs

Research in ATI © Raimund Ubar Each node in SSBDD represents a signal path: The faults at y 3 in HLDD represent the faults in the control circuitry and in the multiplexer M3 of the RTL circuit Fault Collapsing with Structural HLDDs Fault collapsing – not investigated at high-level The faults at R1*R2 in HLDD represent the faults in multiplier, input and output buses, and in the registers

Research in ATI © Raimund Ubar Fault Activation in Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R  0 R 2 IN R Multiple paths activation in a DD Control function y 3 is tested Decision Diagram R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 Data path: Control path Test cycle: Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2

Research in ATI © Raimund Ubar Uniform Conditional Node Fault Model A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Test data calculation rules:  m T  M T (OP): [f(m T )  ZERO)]  m i,m j  M T (OP): [(f(m i )  f(m j )) ≠ f(m i )] Terminal nodes: M T (OP) = {M(A), R(A2), R(A1)+R(A2), R(A1))} Explanation of the meaning of constraints (rules): 1 & & & & R 3 = M(A) R(A1) + R(A2) R(A1) M(A) R(A2) ALU OP=0B= R(A1) M(A) R(A2) In case of fault: R3 = M(A)  R(A2)

Research in ATI © Raimund Ubar Uniform Conditional Node Fault Model High level analog: Constraints for testing a node OP in HLDD: High-level fault model: Logic level analog: Conditional SAF model Defect SAF Condition (constraint) A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Test data calculation rules:  m T  M T (OP): [f(m T )  ZERO)]  m i,m j  M T (OP): [(f(m i )  f(m j )) ≠ f(m i )] Terminal nodes: M T (OP) = {M(A), R(A2), R(A1)+R(A2), R(A1))}

Research in ATI © Raimund Ubar Multi-Terminal BDDs D C q c q’ D Multi-Terminal BDDs for representing uncertainties: D Flip-Flop RS Flip-Flop JK Flip-Flop S J q R C K c q’ S R q’q’ K J S C q R c S R q’q’ R U U - unknown value 44

Research in ATI © Raimund Ubar Generalization of MTBDDs for FSMs 1/0 3/0 5/0 6/1 4/1 2/1 x1 x2 x1 Res State Transition Diagram: New features: representing vectors (vector DD) multi-output internal nodes multi-terminal DDs 45