ETD/Online Summary D. Breton, U. Marconi, S. Luitz Frascati Workshop 04/2011

Main items of discussion this week Synchronous, Pipelined, Fixed-Latency 2

Reminder of a few system parameters as of today The maximum trigger rate is 150 kHz, with a latency of 6µs. Dead-time minimum trigger spacing < 70 ns. The estimated event size at the FE is 500 kB. We set the aggregate input rate for one ROM to 10 Gb/s. Number of FEE 1.8Gb/s data links : 325 With these assumptions the number of ROMs needed to manage the SuperB data flux can be estimated to be of the order of: (8. × 500. ×10 3 ) × (150. × 10 3 )/(10. × 10 9 ) = 60 boards Each ROM will handle ∼ 10 kB of fragment size at 150 kHz.

Irradiation of the event data SERDES chipset (TLK2711 => was performed => results are less good than for the clock and control chipset (DS92LV18) Chip is easier to handle But sensitivity to radiation is higher, both in dose and single event effects, probably due to its older technology It stops functionning after ~ 75 krads However, annealing is fast and the chip rapidly becomes functional again => behaviour has to be studied with a very low rate in order to see if annealing may compensate the increasing dose in real time We have to define plans to start qualifying components of the optical layer The use of mezzanines vs firmware blocks should be discussed again for the FCTS and ROM sides, because of the lack of available physical space in some new implementations Clock and control links Dynamic currentStatic currentAnnealing of dynamic current Effect of the integrated dose and annealing on the current consumption

First simulations of a model of the front-end derandomizer have been presented by Steffen This interesting exercise allowed us to get a first idea of the necessary depth A more complex simulation, based on actual hardware implementation, is currently being performed by Jihane  results will be presented at Elba  the goal here is to give to subdetectors a table with the necessary derandomizer depth and number of bits per event per link with respect to the width of their own trigger time window Common Front-End Electronics

Universal AMC board could be used for: FCTS master FCTS link distribution FCTS throttle ECS master ROM A few number of boards could be designed for FCTS, ECS and Acquisition system: AMC board MCH tongue 2 and 3&4 (but some CCPM & CERN development could be used) 2 or 3 mezzanines Daniel presented a new possibility of implementation of the FCTS electronics, using a µ-TCA format. FCTS

Since Caltech, new steps were made in understanding the solution to be described in the TDR. We had a presentation from Marco describing the two possible approaches to the implementation of the ROM: Based on custom electronics and field busses: using FPGA to get data from the FEE, perform “simple” synchronous processing, and format data according to a suitable industrial standard. Based on custom electronics and host PC/CPUs: FPGA being used to get data from the FEE (possibly perform synch. Processing) and inject them into the PC via PCIe. CPUs will perform complex data processing and data transfer, using standard protocol and on board network interface cards. We have to refine the ratio price/performance/flexibility of the two solutions. ROM

At this time of the project, trigger is the less advanced item inside the scope of ETD The main question is linked to the trigger time jitter, which has a direct influence on the dataflow, especially for sub-detectors with short window and lots of data (like SVT) => What is the best achievable time precision for the trigger primitives ? Barrel EMC is the weak point in this matter => it is urgent to study its best possibilities in terms of time precision (new preamplifier on CSI) We need to perform simulations of new algorithms => it is urgent to find a solution to this end We would like to standardize the philosophy of the primitives between DCH and EMC EMC primitives could be simply encoded on LVDS copper pairs towards intermediate boards were digital encoding of time and energy could be performed DCH could fit to this scheme, thus freeing the return path of the clock and control links for the transfer of loss of lock and throttle toward FCTS system Trigger

SVT Striplets baseline option : –Better physics performance  Readout chip in the planning phase –Upgrade to pixel, more robust against background, foreseen for a second generation of Layer 0  Readout chip already designed Layer 0 Triggered FE chips Layer 1-5 Strip detectors  Readout chip in the planning phase Triggered FE chips FE Ctrl logic Buf #k... Buf #1 ADC Or ToT BUF #1 readout/slow control strip #127 strip #0 FE Ctrl logic Buf #k... Buf #1 ADC Or ToT Sparsifier ~hit_rate * trig_latency Triggered hits only Strip RO chip DAQ Chain main activities RadHard SerDes needed

DCH  DCH prototype front-end and HV distribution boards have been already designed. Boards production will start within one week.  DCH prototype will be used to verify cluster counting implementation both using fast digitizer and derivative circuit.  A new version of derivative circuit has been designed and simulated using (as stimulus file) data acquired by means of DRS digitizer. Simulation with Garfield data are going on to tune circuit parameters.  Readout chain requires large use of programmable logic (FPGA) including the TDC design, then both accurate study of background radiation and radiation tolerant design are required (in this design off-detector readout chain is located near the detector)  Up to now attention was focused on off-detector front-end electronics, nevertheless preamplifiers to amplify wire signals are also needed …

PID Forward PID studies FARICH Preliminary design of electronics was presented: hard constraints => space/ cooling. Fast FPGA could be used as TDC (~ 2ns resolution )  DCH talk at FE session FE ASIC: several candidates: DIRC ASIC / NINO13 chip  Main remark: careful study has to be done on the radiation level at this location (Total dose, particle flux) FPID Run 4 on the CRT with mylar between tube and bars to reduce number of photons. Complete agreement with Geant4 simulation and data => 70 ps rms resolution Barrel Test benches Test boards under design: harmonization of the electronics designs for the different test Bari, Orsay, SLAC. Development tools for data analysis for CRT and future electronics chain. Detector oriented electronics “Young researcher project “( N. Arnaud ) submitted on PID French founding agency : 130 k€ -> answer July FE analog chip: PIF: under design – successful preliminary simulations performed. FE TDC (70ps rms resolution): SCATS: under design – simulations & layout ongoing. Submission July 2011.

EMC  Test bench activities go on => goal is to better understand the crystal response  There is a high priority in understanding the best time resolution achievable with CSI  The electronics worked well during the CERN test beams and noise source are understood (shaper)  An important activity is devoted to the optimization of the design for both trigger primitives and event data  a dual shape system is proposed.  a Pulse Width Modulation implementation is proposed for the trigger link encoding Primitive towers from FEMC

We had lively discussions during the three full sessions. Common involvement is rising. System definition is stable, but its implementation is evolving (FCTS, ECS, ROM…) There is some concern about the readout link serializer concerning radiation hardness => extra work is needed to understand the low dose behaviour We have to study how to deal with luminosities above (our current safety margin for 150 kHz trigger rate is ~ 50%) There is still a lot of work to be done on the trigger side for the TDR => performing simulations would be of great help First feedback from radiation flux simulations were presented. This work has to be pursued in order to obtain reliable numbers. We should get such an information at Elba meeting. Conclusion