Electronic and Information Engineering Department (DIEI) Slide 1 Euro Sereni (presenter) Giuseppe Baruffa, Fabrizio Frescura, Paolo Antognoni A SOFTWARE RE-CONFIGURABLE ARCHITECTURE FOR 3G AND WIRELESS SYSTEMS Department of Electronic and Information Engineering (DIEI) - University of Perugia - Via G. Duranti , Perugia, Italy, {sereni, baruffa, Digilab 2000 Via A. Vici z.i. La Paciana 06034, Foligno (PG), Italy,

Electronic and Information Engineering Department (DIEI) Slide 2 Summary Mobile and wireless communications scenario Software Radio for transceivers: a winning choice The implementation testbed –Digital Base Band –Analog Radio Frequency Selection of communication standards Conclusions and future work

Electronic and Information Engineering Department (DIEI) Slide 3 Mobile and wireless communications Current generation wireless technology requires: the use of different terminals dedicated applications for each standard UMTS /Hiperlan GPRS Bluetooth Next generation software radio technology will provide: the use of a single terminal integrated applications for the different standards GPRS UMTS /Hiperlan Bluetooth

Electronic and Information Engineering Department (DIEI) Slide 4 3G and Wireless-LAN scenario. WLAN services offer new business opportunities to service providers, and a comprehensive solution with GPRS and UMTS networks would provide users with flexibility and portability. The standards currently in the market are GPRS, IEEE802.11/b and Bluetooth. Third generation standards (UMTS and IEEE802.11/a) will provide high data rate radio access and they will allow new and more complex services. From a digital point of view, the complexity of re-configurable systems will depend on the possibility to implement an appropriate software library. The reprogramming ability of the hardware platform (i.e. DSP/FPGA) will guarantee the system re-configuration.

Electronic and Information Engineering Department (DIEI) Slide 5 Software Radio terminals The software radio terminals must be auto re-configurable, in order to match the different telecommunication standards. Software Radio (SWR) defines a radio system capable to change its radio parameters by software rather than by hardware, such as: –operating frequency range –bandwidth –level of power –type of modulation –channel coding –ecc.. Powerful Digital Signal Processors are needed to implement the demanded re-configurability

Electronic and Information Engineering Department (DIEI) Slide 6 Ideal Software Radio system Software Radio Transceiver, in its widest meaning, defines a general TX/RX architecture directly operating on an RF digitized information stream, which can be completely reconfigured by software. The Analog to Digital conversion (ADC) is moved as near as possible to the antenna. SWR capability to support different standards is mainly due to: –The range of frequencies and bandwidth of the RF stage; –The greatest bandwidth assigned to a signal; –The sampling frequency of the ADCs; –The maximum dynamic range; –The computational capability of the digital processors (DSP in general, and FPGA). DSP RF HPA LNA ADC DAC

Electronic and Information Engineering Department (DIEI) Slide 7 Receiver Architecture Analog processing is limited at the RF front-end (pass-band filter + LNA) The ADC generates a digital RF stream that is fed to a RF-BB DSP subsystem that: –Centres the received signal spectrum to the band of services of interest; –Lowers the sampling frequency of the digital stream down to the required standard rate; –Operates the necessary digital filtering in order to reject the unwanted adjacent signals; –Demodulates, channel- and source-decodes the symbol flow. However, this architecture is unfeasible for nowadays technology –The analog RF stage should operate in a range varying from hundreds of MHz to tens of GHz. –The required precision and sampling rate impose severe constraints on the ADC.

Electronic and Information Engineering Department (DIEI) Slide 8 Software Radio Transceiver Architecture Nowadays, the technology does not allow having a digital RF stage (Digital Front-End), so the SWR transceiver uses different analog RF stages, one for each considered standard.

Electronic and Information Engineering Department (DIEI) Slide 9 Optimisation issues for 3G and Wireless systems The number of bit in the ADC and DAC converters. –ADCs show an exponential relationship between resolution and dissipated power. –The processing area and power consumption are a polynomial function of the number of bits. –Careful selection is required for power control and AGC subsystems. The splitting of processing functions between the ASIC and the DSP. –Implementing functions on ASIC, does not always help to reduce space and power consumption, since different functions correspond to increased ASIC area. –The number of functions performed by the DSP should be maximised in order to maintain an high degree of flexibility. The impact on the radio performance of different sub optimal algorithms. –Any sub optimal algorithm must be carefully evaluated with respect to the ideal case, because any degradation leads directly to increased power requirements for transmission and/or to a reduced sensitivity of the receiver

Electronic and Information Engineering Department (DIEI) Slide 10 Software Radio Transceiver Activity Plan 1Q022Q023Q024Q02 1Q02 2Q02 3Q02 4Q02 Software Hardware C6202 IEEE802.11/a 1Q03 2Q03 IEEE802.11/b UMTS 2Q03 System Integration + Bluetooth module Commercial RF Integration Commercial RF Integration C ASIC Viterbi Decoder 2 DSPs C6202 PCI board Bluetooth protocol stack GPRS RF module + ASIC/ FPGA Module 2 DSP C6416 PCI Board C6416 PCI Board

Electronic and Information Engineering Department (DIEI) Slide 11 Baseband Software Radio Hardware Testbed (1/2) For the selected systems (IEEE \a, UMTS, GPRS), a PCI hardware testbed has been devised, based on two DSPs and one Forward Error Correction device. This board can provide for high computational capability, straightforward utilization and trouble-free modularity. Main hardware features are: –Two fixed-point 250 MHz TMS320C6202 DSPs (4.000 MIPS) –One Reed-Solomon and Viterbi decoder (up to 62 Mbit/s) –1 Mbit,125 MHz, Dual Port SRAM –32 Mbit, 125 MHz, SBSRAM –One PCI Bridge, with 66 MHz 32-Bit PowerPC RISC CPU Core –128 Mbit external SDRAM –PCI Daughter board standard expansion connectors. –Bluetooth external module

Electronic and Information Engineering Department (DIEI) Slide 12 Baseband Software Radio Hardware Testbed (2/2) Bluetooth Module

Electronic and Information Engineering Department (DIEI) Slide 13 RF Software Radio Hardware Testbed (1/2) A dual-band ([ MHz] or [2.025 – 2.5 GHz]) software selectable quadrature modulator, has been selected, : –Tx Front-End Dual 40 MHz 10-bit DAC converters 6-pole Butterworth clock rejection filters Low phase-noise frequency synthesizer programmable in steps of 100 KHz Output power can be controlled using 10-bit control words (Non-linear scale) Selectable internal/external 10 MHz frequency synthesizer –Rx Front-End Sensitivity: -56 dBm RF input for full scale 10-bit output samples Built-in AGC, 70 dB dynamic range. Low phase-noise frequency synthesizer programmable in steps of 100 KHz Dual 10-bit ADC, 40 Msample/s Two base band filter options, for Narrow-band (<300 KHz) or Wideband (<20 MHz) applications

Electronic and Information Engineering Department (DIEI) Slide 14 RF Software Radio Hardware Testbed (2/2) RF out Tx power control 90deg 0deg + Frequency Synthesizer I Q frequency selection 10-bit DAC Low-Pass Filter 10-bit DAC Low-Pass Filter Data I In Data Q In Sample clk in 90deg 0deg Frequency Synthesizer ~~~~ ~~~~ 10-bit ADC Data I out Data Q out 40 Mhz oscillator RF In frequency selection Digital clock out AGC

Electronic and Information Engineering Department (DIEI) Slide 15 Physical layers of IEEE \a, UMTS, and GPRS, at the transmitter side (1/2) IEEE \a: because of the high throughput of this WLAN standard (up to 54 Mbit/s), a dedicated unit has to realize OFDM modulation (i.e. an IFFT operation) and Viterbi decoding. This is the most computationally demanding standard. UMTS: according to 3GPP, the spreading requires an ASIC/FPGA device or a very powerful DSP (such as, for example, TMS320C64x), while encoding, interleaving and rate matching are carried out by a less performing DSP GPRS: a single DSP unit is sufficient. Similarities with GSM are exploitable to implement it.

Electronic and Information Engineering Department (DIEI) Slide 16 Physical layers of IEEE \a, UMTS, and GPRS, at the transmitter side (2/2) Higher Layers Interface IEEE UMTS Convolutional Encoder rate 1/2, K = 7 Puncturing rate 2/3, 3/4 Block Bit Interleaving Mapping BPSK, QPSK, (16/64)-QAM IFFT + Guard Band Addition Symbol Shaping Scrambling Convolutional Encoder rate 1/2, 1/3 Rate Matching Block Bit Interleaving Segmentation + Multiplexing Block Bit Interleaving CRC + Segmentation Spreading Amplification Scrambling Block EncoderPrecoding and Tail Convolutional Encoder rate 1/2, K = 4 Puncturing rate 2/3, 3/4 Block Interleaving GPRS BB - IF Interface

Electronic and Information Engineering Department (DIEI) Slide 17 IEEE \a testbed Software Architecture DSP 1 DSP 2 DSP 1 Puncturing BPSK QPSK 16-QAM 64-QAM BPSK QPSK 16-QAM 64-QAM Bit Interleaving Bit Interleaving Convolutional Encoder Convolutional Encoder Pilot carrier Insertion Pilot carrier Insertion Viterbi Decoder Viterbi Decoder De- Interleaving DSP 2 Channel Equalization FFT Data Input De- Puncturing De- Puncturing Data Output Base Band Input IFFT Base Band Output Demapping Symbol Timing Sync. Tx Side Rx Side

Electronic and Information Engineering Department (DIEI) Slide 18 IEEE a Computational Complexity

Electronic and Information Engineering Department (DIEI) Slide 19 Conclusions A modular architecture for implementing mobile and wireless communications standards and for evaluating their complexity as been introduced. The adoption of reconfigurable computing devices allows testing several air interfaces simply by uploading a new program on the testbed system The testbed can be used to study the feasibility of future software radio systems The results achieved have been considered and shown