Multicore CPU with Multi-Threading Operating Environment

Overview Team Goals Job Distribution Multicore IRQ WriteBackBuffer BlockRAM CLK4x Generic Memory Arbiter

Marcel Schaal Benedikt Weber Bastian Reitschuster Rudolf Netzel Team

Goals Dual core CPU WriteBackBuffer double Mandelbrot in split screen

Job Distribution Bastian + Rudolf WriteBackBuffer Interrupts Marcel + Benedikt Multicore CPU implementation OS + hase research

Problems Not enough Block RAMs Overclocking register file Number of read/write ports Timing is everything Clock skew and routing delay Only 24h a day Softwareenvironment

Multicore Architecture

WriteBackBuffer Why? Speedup Store-Instructions How? Buffer data and addresses in FIFO writing buffered elements into memory whenever possible

WBB implementation Using one BlockRAM for the WriteBackBuffer Two read and write ports needed Two read and write operations per cycle Internal read- and writepointer

WBB – first design

WBB - FSM

BlockRAM 2W2R Why? 2*32 bit data to write/read but one BlockRAM has only 2*16 bit How? Overclocking BlockRAM four times write A, write B, read A, read B

ERROR Because of limited BlockRAMs and even harder timing constraints Implementation as Distributed RAM with far less entries

BlockRAM 2R1W Why? Simple regfile needs four BlockRAMs Too many for more than four cores How? Again overclocking BlockRAM four times Register Input, Read A, Read B and Write

Generic Memory Arbiter Every core needs access to memory GMA handles memory request Generic in number of ports Similar to memory arbiter of task 2 needed for instruction fetch and load/store unit Round-Robin implementation

System stuff Only the master core can handle interrupts Every Core is able to execute other core Brancher handles execute-opcode (in/out)

Hase Adding new opcodes Don't let anybody see sourcecode Hase counts destination for labels wrong

Sample Video Please wait a moment

Surprise: Multi-Threading Why? Multiplicators need ~10% of boardarea SIMD doesn't utilize multiplicators enough Load-/Store-unit utilization < 1% (Mandelbrot) Less usage of boardarea than Multi-Core Still two weeks of time available It is possible so why not?

Features Generic number of cores, threads and SIMD synchronization unit (lock, unlock, access data) Shared multiplicators and load-/store unit Load-/store scheduler - similar to memory arbiters

Multi-Threading-Core

No final version Everything went wrong Too much timing problems 10ns are hard to achieve (somebody said impossible ) Two weeks are shorter than thought Strange behaviour of XST, Modelsim, boards Old working example doesn't work anymore

Thank You Questions?