CS-EE 481 Spring March, 2005 University of Portland School of Engineering Project Bighorn CMOS Low Pass Switched Capacitor Filter Team Brien Bliatout DeMarcus Levy Sam Russum Advisor Dr. Peter Osterberg Industry Representative Mr. Mike DeSmith

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Overview Introduction to an LPSCF Accomplishments so far Current Issues and Concerns Plans for the future Conclusion

CS-EE 481 Spring March, 2005 University of Portland School of Engineering General LPSCF Schematic

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Purpose of SCFs No Resistors High Accuracy Can be implemented in ICs

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Schematic of Project Bighorn

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Frequency Response

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Transfer Function Equation

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Schematic of Project Bighorn

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Ideal Clock Signal Outputs

CS-EE 481 Spring March, 2005 University of Portland School of Engineering 555 Schematic

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Clock Schematic

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Delay Line Schematic

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Ideal Clock Signal Outputs

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Accomplishments SUCCESS! The Macro-model works.

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results Deliverable to Dr. Osterberg for future EE451 class demonstrations. Ready to test MOSIS chip.

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow = 200mV Input, Blue = Output Spice Simulation

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – Φ 1, Blue = Node 1 Spice Simulation

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – Φ 1, Blue = Node 4 Spice Simulation

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = Node 5 Insert Node 5 and compare to Mike’s Spice Simulation

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out, Roll-off Frequency

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Macro Model

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Layout

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Layout Close-up

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Will MOSIS Chip Work? Why it might not: –On resistance of the transistors are too high τ = RC Why it might: –It is possible that capacitors were sized incorrectly on chip making the capacitors smaller in value.

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Milestone Table

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Concerns/Issues Paper work.

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Plans Test MOSIS chip Prototype Release Final Report

CS-EE 481 Spring March, 2005 University of Portland School of Engineering Conclusion SUCCESS! Paper work is all that’s left.