HCAL upgrade FPGA FW: tasks and issues 12 May2016 Tullio Grassi, Univ. of Maryland

FPGAs in HF, HE, HB igloo2 FPGA Bridge FPGA QIE card ngCCM Various FPGAs, responsibility of U.VA CU (HBHE only) One FPGA, responsibility of K.S.U. Back FPGA Front FPGA uHTR card FC7 card (ngFEC) Various FPGAs, responsibility of DESY AMC13 Various FPGAs, responsibility of B.U. 2 FE electronics BE electronics

Where you can find the fw Source code and programming files are stored on the SVN repository “cms-firmwsrc” at CERN. It is viewable on: For each FPGA, the recommended FW version sometimes is indicated in the folder “tags”, other times it is the latest version in the folder “trunk”. The programming file is often the folder where the development tool generates it. 3

QIE card FW igloo2 FPGA (HF, HE, HB) alignment of QIE channels: started Co-existence of 2014-QIE and 2016-QIE FW Stronger link error-detection TDC-in-FPGA Bridge FPGA (HE, HB): resolve inconsistencies in HE addressing 4

ngCCM FW HF ngCCM: Port the changes to the HE ngCCM back to the HF ngCCM: should make communications more robust Look into Slot 3,4,5 issue that appears to be a firmware issue Update logic to allow for power cycling half of a crate at a time as a way to mitigate the current leakage problem Make use of Fermilab’s 20 GHz oscilloscope to tune the VTRx signals to/from the Igloo2 on the mezzanine Update to the latest CERN-made GBT firmware ? HE ngCCM: perhaps add monitoring features (communications lost counter, automatic reset counter, etc) any changes to support production board changes determine why some ngCCMs have communication problems and others do not - board assembly issue? SERDES tuning issue? test the redundancy feature Update to the latest CERN-made GBT firmware ? 5

HE Calibration Unit FW Need clarifications (failure of DC-DC converters, address map) 6

FC7 FW No issues at the moment Expect we need support (modifications) during runs 7

uHTR FW Port input link improvements to HF and HBHE at 4.8 Gbps (2 weeks FTE) Mixed HBHE firmware with 1.6 (legacy) and 5 Gbps (upgrade) links (3 weeks FTE) TPG blocks for legacy HB – upgraded HE FE (>5 weeks FTE)  Fiber mapping still not decided, firmware development on hold TPG blocks for full HBHE upgraded FE (>5 weeks FTE)  Fiber mapping still not decided, firmware development on hold Bugs in the Trigger Primitives on 1.6 Gbps uHTR (for legacy FE) 8

Problems and other considerations “Zero-data events” problem [in bld904: elog/ In Point5: ] elog/915401http://cmsonline.cern.ch/cms-elog/ FE FPGAs will be exposed to radiation. Radiation mitigation techniques in the FW should be reviewed. …