Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina

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Presentation transcript:

Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina Department of Electronics and Communications Engineering Faculty of Engineering – Cairo University

10/2/2016© Ahmed Nader, MOS: Subthreshold (Weak Inversion) Subthreshold Conduction: For V GS near V TH, I D has an exponential dependence on V GS : Max transconductance efficiency Used for low currents & low frequency applications

10/2/2016© Ahmed Nader, MOS: Intrinsic Capacitance C1 is the gate-channel capacitance C2 is the channel-bulk depletion capacitance C3 & C4 is the overlap gate-source(drain) capacitance C5 & C6 is the source/drain –bulk junction capacitance (bottom- plate and sidewall) Note that junction capacitors are voltage-dependent (non-linear)

10/2/2016© Ahmed Nader, MOS: Intrinsic Capacitance

10/2/2016© Ahmed Nader, MOS Device as a Capacitor: Varactor Assignment 1a: There is a special device with n-doping in an NWELL. Plot the characteristics of such a device. Comment on its properties.

10/2/2016© Ahmed Nader, Small Signal Model The slope of the diode characteristic at the Q-point is called the diode conductance and is given by: g d is small but non-zero for I D = 0 because slope of diode equation is nonzero at the origin. Diode resistance is given by:

10/2/2016© Ahmed Nader, Small Signal Operation of a Diode Subtracting I D from both sides of the equation, For i d to be a linear function of signal voltage v d, This represents the requirement for small-signal operation of the diode.

10/2/2016© Ahmed Nader, Current Controlled Attenuator Magnitude of ac voltage v o developed across diode can be controlled by value of dc bias current applied to diode. From dc equivalent circuit I D = I, From ac equivalent circuit, For R I = 1 k , I S = A, If I = 0, v o = v i, magnitude of v i is limited to only 5 mV. If I = 100  A, input signal is attenuated by a factor of 5, and v i can have a magnitude of 25 mV.

10/2/ Small-Signal Model of a MOS (Two-Port Model) Using 2-port y-parameter network, The port variables can represent either time-varying part of total voltages and currents or small changes in them away from Q-point values.

10/2/ Small-Signal Model of a MOS Since gate is insulated from channel by gate-oxide input resistance of transistor is infinite. Small-signal parameters are controlled by the Q-point. For same operating point, MOSFET has lower transconductance and lower output resistance that BJT. Transconductance: Output resistance:

MOS Transistor © Ahmed Nader, /2/2016 Important Trade-Offs!! Gain Vs. Current Gain Vs. Speed Gain Vs. Voltage Swing

MOS Transistor © Ahmed Nader, Small Signal Model: Body Effect 10/2/2016 Drain current depends on threshold voltage which in turn depends on v SB. Back-gate transconductance is: 0 <  < 1 is called back-gate tranconductance parameter.

10/2/2016© Ahmed Nader, Small-Signal Model of a MOS: High Frequency Model Voltage dependent current source (g m V gs ) models dependence of drain current on gate-source voltage Output resistance models dependence of drain current on drain- source voltage (channel length modulation) Voltage dependent current source (g mb V bs ) models dependence of drain current on bulk-source voltage (body effect)

MOS Transistor © Ahmed Nader, Useful Model Small Signal: /2/2016

MOS Transistor © Ahmed Nader, Special Cases Bias point 10/2/2016

© Ahmed Nader, Deep Sub-Micron Technologies

10/2/2016© Ahmed Nader, Analog Low-voltage – High- Speed trade-off Fixed for the technology and fixed L

10/2/2016© Ahmed Nader, Deep Sub-Micron Technologies Some small geometry effects: 1- Gate leakage 2- Threshold voltage variation 3- Output impedance variation with V DS (non-linearity ) 4- Mobility degradation with vertical field 5- Velocity saturation 6- Reliability Effects (GO, Hot Carrier, NBTI,..) 7- Stress Effects (STI, Well Proximity,..) Assignment 1b: Choose one of those effects in 6 or 7 and describe it in details (physical meaning, effect on performance, etc.)

10/2/ Deep Sub-Micron Technologies © Ahmed Nader, 2013 What about scaling of V th ?

10/2/2016© Ahmed Nader, Deep Sub-Micron Technologies – Mobility degradation with Vertical Field Carriers are confined to a narrower region below oxide- silicon interface leading to more carrier scattering and hence lower mobility Assignment 1c: Find an expression for HD3

10/2/2016© Ahmed Nader, Deep Sub-Micron Technologies – Velocity Saturation

10/2/2016© Ahmed Nader, Deep Sub-Micron Technologies – Velocity Saturation

10/2/2016© Ahmed Nader, MOS Device Models Level 3 Model BSIM (Berkeley Short-Channel IGFET Model)

10/2/2016© Ahmed Nader, MOS Device Models

10/2/2016© Ahmed Nader, Analog Layout

10/2/2016© Ahmed Nader, Analog Layout

10/2/2016© Ahmed Nader, Analog Layout

10/2/2016© Ahmed Nader, Analog Layout Adding Dummies. How can dummies help in STI? Connect gate (poly) from both sides

10/2/2016© Ahmed Nader, Analog Layout: Inter-digitation

10/2/2016© Ahmed Nader, Analog Layout

10/2/2016© Ahmed Nader, Analog Layout: Common Centroid

10/2/2016© Ahmed Nader, Analog Layout

10/2/2016© Ahmed Nader, Resistor Layout

10/2/2016© Ahmed Nader, Capacitor Layout

10/2/2016© Ahmed Nader, Inductor Layout

10/2/2016© Ahmed Nader, Inductor Layout Spiral Inductor Calculator (Stanford): Assignment1: Using ASITIC tool: Design an Inductor with L=2nH and Q>10

10/2/2016© Ahmed Nader, Analog Layout: Summary

10/2/2016© Ahmed Nader, Analog Layout: Example

10/2/2016© Ahmed Nader, Analog Layout: Example