E. Hazen1 New DCC Status and Software issues Eric Hazen, Phil Lawson, Shouxiang Wu, Jim Rohlf, Arno Heister, Jason StJohn Boston University

E. Hazen2 New DCC Overview Single board; 15 HTR spigots, Ethernet, TTC, TTS on front Optional P3 rear transition module for i.e. future selective readout

E. Hazen3 Current Status 10 Prototypes assembled Essentially all hardware tested including HTR/DCC links (error-free!) Waiting for updated register map from Mr Wu.... Software work progressing (details follow)

E. Hazen4 Hardware Changes Two address regions: VME control atA24 (slot<<19) same as HTR All else atA32 (slot << 27) Most A32 registers very similar to old DCC Will maintain old HAL names where possible CfgScript changes should be few (but we must handle differences) New configuration scheme One large standard parallel flash chip for all FPGAs Much faster programming than old DCC w/ LRBs

E. Hazen5 Software Goal: plug-compatible with old DCC One crate may contain both old and new DCC! How to manage this? Current hcalDCC class becomes a wrapper DCC1 and DCC2 classes represent old/new boards All current methods will exist at least as stubs Strategy Add new classes to CVS very soon so new releases will have this structure to avoid divergent code Add functionality to DCC2 class as it is developed Who is doing it? Phil, Eric, Arno, Jason

E. Hazen6 Software Changes DCC2 class will be much simpler than DCC1 class Core functions the same, just simpler details Framework in place, DCC2 class partially implemented DCCManager (initial work done) Must support both types with no externally-visible differences A few CfgScript changes. Monitoring will be a bit of a challenge Some items change size (8-32 bits), some disappear, some new How to handle this? Make a monitoring DB schema which can accept both (Jason)

E. Hazen7 Software Changes Continued Firmware DB 3 new firmware types (VME, Xilinx, LRB) New/upgraded command-line utilities DCCdiagnose (re-write or support both?) DCCProgrammer (re-write or support both?) DCCRepair (not needed, we hope!) HyperDAQ Must support both

E. Hazen8 Plans / Schedule Schedule milestones: Preliminary documenation from WuWeek of 2/9 Essential DCC2 methods implementedWeek of 2/23 Taking data with xDAQ Week of 3/1 Initial testing in 904 Week of 3/16

E. Hazen9 Backup

E. Hazen10 New DCC VME64 Interface Etherne t TTS TTC 3 HTR Inputs Event Builder TM Connector (future opt.) Slink (back side)