Topics Wire and via structures. Wire parasitics..

Slides:

Advertisements

Similar presentations

MICROWAVE FET Microwave FET : operates in the microwave frequencies

Advertisements

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

UNIT 4 BASIC CIRCUIT DESIGN CONCEPTS

EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.

Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout.

VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.

Lecture 11: MOS Transistor

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 3 - Transistors,

Lecture 15 OUTLINE MOSFET structure & operation (qualitative)

Lecture 10: PN Junction & MOS Capacitors

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory

The metal-oxide field-effect transistor (MOSFET)

Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.

Lecture 24: Interconnect parasitics

Circuit characterization and Performance Estimation

ECE 424 – Introduction to VLSI Design

Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;

ECE 342 Electronic Circuits 2. MOS Transistors

２． Transistors and Layout Fabrication techniques Transistors and wires Design rule for layout Basic concepts and tools for Layout.

EXAMPLE 6.1 OBJECTIVE Fp = 0.288 V

EE 4345 Chapter 6 Derek Johnson Michael Hasni Rex Reeves Michael Custer.

EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

NMOS PMOS. K-Map of NAND gate CMOS Realization of NAND gate.

Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003.

Structure and Operation of MOS Transistor

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire and via structures. n Wire parasitics. n Transistor parasitics.

VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.

1 Interconnect/Via. 2 Delay of Devices and Interconnect.

Introduction to MOS Transistors Section Outline Similarity Between BJT & MOS Introductory Device Physics Small Signal Model.

VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA

CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Bipolar transistors.

CMOS VLSI Design CMOS Transistor Theory

UNIVERSITI MALAYSIA PERLIS

CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.

Integrated Circuit Devices

Introduction to CMOS VLSI Design CMOS Transistor Theory

CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from.

Introduction to MOS Transistors

Power Distribution Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.

Chapter 6 The Field Effect Transistor

Derek Johnson Michael Hasni Rex Reeves Michael Custer

MOS Capacitance Unit IV : GATE LEVEL DESIGN VLSI DESIGN 17/02/2009

Circuit characterization and Performance Estimation

Recall Last Lecture Common collector Voltage gain and Current gain

Prof. Haung, Jung-Tang NTUTL

Metal Semiconductor Field Effect Transistors

Revision CHAPTER 6.

CMOS Devices PN junctions and diodes NMOS and PMOS transistors

Unit IV: GATE LEVEL DESIGN

6.3.3 Short Channel Effects When the channel length is small (less than 1m), high field effect must be considered. For Si, a better approximation of field-dependent.

Depletion Region ECE 2204.

Current Flow ECE 2204.

Physics 122B Electricity and Magnetism

Lecture 5 OUTLINE PN Junction Diodes I/V Capacitance Reverse Breakdown

Lecture 16 ANNOUNCEMENTS OUTLINE MOS capacitor (cont’d)

Magnetostatics.

Lecture 7.0 Device Physics.

Device Physics – Transistor Integrated Circuit

MOSFETs - An Introduction

Lattice (bounce) diagram

Device Physics – Transistor Integrated Circuit

CP-406 VLSI System Design CMOS Transistor Theory

Lecture 7.0 Device Physics.

Lecture #15 OUTLINE Diode analysis and applications continued

Measuring Current.

Semiconductor Diodes Introduction Diodes

Power distribution.

Dr. Hari Kishore Kakarla ECE

Presentation transcript:

Topics Wire and via structures. Wire parasitics.

Wires and vias metal 3 metal 2 vias metal 1 poly poly p-tub n+ n+

Metal migration Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

Metal migration problems and solutions Marginal wires will fail after a small operating period—infant mortality. Normal wires must be sized to accomodate maximum current flow: Imax = 1.5 mA/m of metal width. Mainly applies to VDD/VSS lines.

Diffusion wire capacitance Capacitances formed by p-n junctions: sidewall capacitances depletion region n+ (ND) bottomwall capacitance substrate (NA)

Depletion region capacitance Zero-bias depletion capacitance: Cj0 = si/xd. Depletion region width: xd0 = sqrt[(1/NA + 1/ND)2siVbi/q]. Junction capacitance is function of voltage across junction: Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

Poly/metal wire capacitance Two components: parallel plate; fringe. fringe plate

Metal coupling capacitances Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1 metal 1

Wire resistance Resistance of any size square is constant:

Metal mean-time-to-failure MTF for metal wires = time required for 50% of wires to fail. Depends on current density: proportional to j-n e Q/kT j is current density n is constant between 1 and 3 Q is diffusion activation energy

Skin effect At low frequencies, most of copper conductor’s cross section carries current. As frequency increases, current moves to skin of conductor. Back EMF induces counter-current in body of conductor. Skin effect most important at gigahertz frequencies.

Skin effect, cont’d Isolated conductor: Conductor and ground: Low frequency Low frequency High frequency High frequency

Skin depth Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: d = 1/sqrt(p f m s) f = signal frequency m = magnetic permeability s = wire conductivity

Effect on resistance Low frequency resistance of wire: Rdc = 1/ s wt High frequency resistance with skin effect: Rhf = 1/2 s d (w + t) Resistance per unit length: Rac = sqrt(Rdc 2 + k Rhf 2) Typically k = 1.2.

Wire capacitance and resistance Capacitance to ground (aF/mm) Coupling capacitance (aF/mm) Resistance/ length (W/mm) Metal 3 18 9 0.2 Metal 2 47 24 0.3 Metal 1 76 36

Gate delay vs. wire delay Minimum-size inverter delay: 2.9 ps Length of wire with equal delay---assume wire with capacitance equal to inverter input capacitance = 0.12 fF. Metal 3 length is 6.7 mm. About 75 times width of minimum-size transistor.