E. Hazen - Back-End Report1 AMC13 Status Update ● Version 1 (5Gb/s links, Virtex-6 chip) ● 15 modules built, all but 3 distributed to colleagues ● 1 at P5 participating for Slice test ● Version 2 (10Gb/s links, Kintex-7 chip) ● Design ready to send out, expect to send in next days. – Brief delay to study different high-speed base material options for PCB to ensure 10GB operation ● Prototypes expected in mid-January 2 pcs initial for lab testing 15 pcs total to produce (aim: yield > 12)

E. Hazen - Back-End Report2 AMC13 Rev 2 Changes ● Virtex 6 to Kintex 7 for 10G link support ● Two-way GbE switch removed, GbE to Spartan chip only ● (Never used Virtex GbE option) ● SDRAM size increased from 128MB to 512MB speed to 800MHz DDR (1600MT/s * 16 bits) ● Clock source changes: ● Rev 1 used 2x Si570 programmable XO ● Rev 2 uses Si5338B Quad programmable clock generator ● TTC Recovered clock to clock-capable input on Kintex 7 ● Changes to T1-T2 board connector pinout ● Maintain plug compatibility with existing connector ● Add 1 pin for additional 12V to be routed to T3 (plus additional GND) ● There are two diff pairs unused (GPIO pairs) unused for CLK, TTC

E. Hazen - Back-End Report3 Slice Test ● MicroTCA Crate installed with AMC13 and mCTR2 ● Firmware and software in place ● Full DAQ firmware for mCTR2c and AMC13 ● Full xDAQ control and readout software ● Runs taken at P5! ● Bunch structure seen ● LED and laser runs taken and verified ● Parasitic collider run taken and being analyzed – 25 events captured by HLT via normal CDAQ and saved (save 1/2^20 L1A) – 28 events captured by uTCA monitor buffer – EvN, OrN and BcN match (there is a BcN offset...) – Working on matching of QIE data... not as expected, but maybe a software issue. ● Data format very close to VME, so CMSSW analysis chain should work without much trouble on uTCA data uTCA crate at P5 with AMC13 and 6 mCTR2