SCT Links Operation Performance from QA and operation

Slides:



Advertisements
Similar presentations
The latest n-XYTER Test Results Krzysztof Kasiński (AGH Kraków) CBM Collaboration Meeting Acknowledgements: Paweł Gryboś, Robert.
Advertisements

In situ testing of detector controllers Roger Smith Caltech
1 Alan Barr, UCL Fixed Frequency Trigger Veto The problem: –Currents in wire bonds in presence of strong magnetic fields –DC current not a problem (small.
Richard Kass IEEE NSS 11/14/ Richard Kass Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector K.E. Arms, K.K. Gan, M.
Detector lecturesT. Weidberg1 Opto-electronics Why use opto-electronics –General advantages –HEP experiments Elements of system –Emitters –Fibres –Receivers.
Atlas SemiConductor Tracker Andrée Robichaud-Véronneau.
1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Commissioning the ATLAS Silicon Microstrip Tracker IPRD08 - Siena Jose E.
Range Measurement Unit Messenger Mercury Laser Altimeter Basic Familiarization.
VCSEL Failures in ATLAS T. Flick, University of Wuppertal TWEPP 2010 Aachen,
LightABLE Production Status ID Week October 2014 Tony Weidberg1.
Performance of SPIROC chips in SKIROC mode
The ATLAS Pixel Detector - Running Experience – Markus Keil – University of Geneva on behalf of the ATLAS Collaboration Vertex 2009 Putten, Netherlands,
STATUS OF VCSEL BASED OPTO-LINKS JOSHUA MOSS, JENS DOPKE AUGUST 19, 2010 On-going analysis for the on-detector Pixel VCSELs TEMPERATURE MEASUREMENTS OPTICAL.
1 CPC2-CPR2 Assemblies Testing Status Tim Woolliscroft.
1 4 July 2006 Alan Barr - SCT DAQ Experience and plans from running the (SCT) DAQ HEP Setting things up Calibration mode operations Physics mode operation.
A.A. Grillo SCIPP-UCSC ATLAS 10-Nov Thoughts on Data Transmission US-ATLAS Upgrade R&D Meeting UCSC 10-Nov-2005 A. A. Grillo SCIPP – UCSC.
Optoboards dependence on Temperature C. Gemme, T.Flick detector meeting, April 2 nd 2009 Motivations Test in SR1 thanks to K. Lantzsch, L.Masetti, J.Moss,
Optimising Cuts for HLT George Talbot Supervisor: Stewart Martin-Haugh.
5th July 00PSI SEU Studies1 Preliminary PSI SEU Studies Study SEU effects by measuring the BER of the link in  /p beams at PSI. Measure the SEU rate as.
BTeV Pixel Detector Optical link receiver chip Data In and Out project.
1 xCAL monitoring Yu. Guz, IHEP, Protvino I.Machikhiliyan, ITEP, Moscow.
Installation and Testing of Optical Harnesses John Matheson Rutherford Appleton Laboratory Schedule for test and assembly Outline of required tests Acceptance.
Muon commissioning status and plans G.P. C. De Plano.
The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland.
SCT/Pixel Off-detector VCSELs
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
January, 2003CMS Ecal1 MGPA Specification Discussion – 9 th Jan. 03 OUTLINE 3 or 4 gain channels discussion technical background - why 3 gains could be.
Tony WeidbergOpto WG April '081 SCT Links Long Term Monitoring Summary quality installed links Techniques for monitoring long term performance –Data links.
Sensor testing and validation plans for Phase-1 and Ultimate IPHC_HFT 06/15/ LG1.
Anatoli Romaniouk TRT Test manual Some important information p. 2-3Some important information p. 2-3 Noise studies p.4-7Noise studies p.4-7 Operation with.
Peter W. PhillipsATLAS SCT Week, CERN, September/October 2002 Electrical Tests of SCT modules using RODs Peter W Phillips Rutherford Appleton Laboratory.
23/01/2007ID Software Workshop1 SCT performance from the SR1 endcap data Satoru Mima Okayama University ID Software Meeting 23-Jan Noise Study -
Understanding Readout Issues with the Pilot System October Fpix Upgrade Meeting Bora Akgün Will Johns Karl Ecklund Helmut Steininger Jordan Tucker.
1 Back-Of-Crate : BOC Status Oct, 2002 BOC is the optical fibre interface for the ROD Receives module control data from ROD, performs clock-data encoding,
1 4 July 2006 Alan Barr - SCT DAQ Experience and plans from running the (SCT) DAQ at SR1 HEP Cosmics setup Running modes Problems Future.
Noise results from SR1 combined SCT barrel tests Summary of some initial results Alan Barr, UCL Pepe Bernabeu, Valencia.
E.Gushchin,S.Filippov(INR,Moscow) 16 April 2008Calo commissioning meeting CERN PS/SPD LED monitoring system status General status LED signal is used for.
`` ATLAS inner detector JV Els KoffemanAtlas - Inner Detector1 Tracking in solenoid 2 Tesla field – 3 pixel layers with 50 um x 400 um cells – 4.
Beam detectors in Au+Au run and future developments - Results of Aug 2012 Au+Au test – radiation damage - scCVD diamond detector with strip metalization.
Alex Dafinca, Jim Henderson & Tony Weidberg (on behalf of the ATLAS SCT Collaboration) Topical Workshop on Electronics for Particle Physics Perugia, 26.
ASICs1 Drain Current Digitizer Chip (DCD) Status and Future Plans.
F. Odorici - INFN Bologna
LHC Wire Scanner Calibration
vXS fPGA-based Time to Digital Converter (vfTDC)
Firmware Update 29/03/2017 Rebecca Ramjiawan.
DAQ for ATLAS SCT macro-assembly
Experience with DAQ for ATLAS SCT
Status report of the ATLAS SCT optical links
SCT On-detector VCSELs
Cabling Lengths and Timing
USBPix Readout System using FE-I4/A chip Status Update: Finalization of Threshold Tuning and Minor updates Jimin Kim and Austin Piehl Department of Physics.
Damping Ring Kicker Tests at AØ
Shifter Instructions regarding the ZD, Dan Peterson
William Stallings Computer Organization and Architecture 7th Edition
BESIII EMC electronics
Optical links in the 25ns test beam
BOC1 Run Thru: Agenda 14h30 Start CB Local Meeting 16h00 Break for Tea
EECS150 Fall 2007 – Lab Lecture #4 Shah Bawany
Stefan Ritt Paul Scherrer Institute, Switzerland
Debugging EECS150 Fall Lab Lecture #4 Sarah Swisher
Operational Experience with the ATLAS Pixel Detector at the LHC
Quadrupole error localization using Response Fits
Debugging EECS150 Fall Lab Lecture #4 Sarah Swisher
RPC Front End Electronics
The CMS Tracking Readout and Front End Driver Testing
The ATLAS LAr. Calibration board K. Jakobs, U. Schaefer, D. Schroff
Imperial laser system and analysis
PHENIX forward trigger review
Fixed Latency Serial Links with FPGA-embedded SerDes for SuperB
Presentation transcript:

SCT Links Operation Performance from QA and operation Setting up links during operation for barrel and EC. TX RX Operational problems Fatalities Difficulties How can we track performance? Acknowledgements thanks to Peter Phillips, Bilge Demirkoz, Caroline Magrath and Nigel Hessey for discussions of SCT procedures Tony Weidberg Pixel Opto November '06

Performance from QA On-detector VCSEL power Two VCSELs in one opto-package have single VCSEL current setting Spread of power between two VCSELs important. Tony Weidberg Pixel Opto November '06

PIN Arrays & DRX-12 Slow tail to signal limits dynamic range Count bit errors in 32k bit stream Blue region is error free. Slow tail to signal limits dynamic range Saturation of DRX-12 at very high input current ~ 800 mA Tony Weidberg Pixel Opto November '06

RX links dynamic range (1) RX link designed to work at power > 40 mW Only tested on one channel but could operate with negligible BER at 35 mW (no error in 1 hour) Bit Error Rate Scans Different Optical power BER RX DAC

RX links dynamic range (2) Look at range of RXmax/RXmin Can’t set RXmax > 255  Need RXmin < 100  reasonable operating window  RXmax ~ 500  Power ~ 1000 mW Would be better to have a larger range for DRX-12 threshold but can only easily increase this by 20%. Does this help? However system should work over dynamic range > ~ 10. Is this true in practice? Tony Weidberg Pixel Opto November '06

Off-Detector VCSELs High mean power but large spread. Change 10 mA  15 mA increases power by ~50% Tony Weidberg Pixel Opto November '06

Setting Up Links TX links Initially set TX DAC = 165  nominal VCSEL current of 10 mA. Newer TXs have higher fibre coupled power  new default TX DAX = 140 Check IPIN. Adjust if <100 (200) or > 700 (600) mA for barrel (EC). Usually ok after this but if there are problems perform TX DAC scan (see later). Tony Weidberg Pixel Opto November '06

RX Links DC coupled links are more difficult to set-up. Old procedure for barrel Perform RX threshold scan. Send configuration data and repeat for 10 triggers (8000 bits). Change RX DAC value and repeat  coarse scan of BER vs RX DAC. Optimal setting RX_DAC=0.3*RXmin+0.7*RXmax  figure. Works but is slow. Set timing to global value (barrel) or perform RXdelay scan (Endcaps). New method: superfast scan (7s) 2d scan of delay and Rxthreshold in clock/2 mode (ABCD returns 20 MHz clock). Works for most modules but use slower Rxthreshold based on configuration data for problematic channels. Tony Weidberg Pixel Opto November '06

RX threshold Scan Good links  wide operating window. Not typical! Most VCSEL too bright so don’t see top edge of scan. RX_Threshold Errors at low RX DAC are not due to noise but are due to the slow tail in the p-i-n signals (off-detector array). RXmin scales with power Tony Weidberg Pixel Opto November '06 Time Bin

MSR Adjustment (1) Need accurate 50:50 MSR for 20 MHz clock  low jitter BC clock recovered by DORIC  don’t try to design perfect clock but allow for adjustments with MSR register. Adjustment will be required on all channels to optimise timing but if it is very wrong can cause problems even in calibration runs. i/p clock with non 50:50 MSR o/p clock has large jitter Tony Weidberg Pixel Opto November '06

MSR Adjustment (2) MSR adjustment can work  produce low jitter BC clock. Obtain jitter (full width) < 0.5 ns for optimal MSR but jitter could be very big if MSR wrong Warning: we found a few VCSEL arrays that had very low MSR and could not be tuned to give 50:50 MSR Register

MSR Adjustment (3) How to set MSR values in full system? MSR scan Idea is to tune system so that duty cycle of clock/2 is independent of BPM phase. MSR scan (1) Set clock/2 mode (2) SetMSR value (3) Measure width of on period with scan of RXdelay. (4) send odd number of bits (SR) of TTC data to flip phase of BPM signal and repeat (3) (5) Change MSR register  3 (6) Plot duty cycle for the two phases as a function of MSR register  figure Plan to develop faster 2D scan in future Tony Weidberg Pixel Opto November '06

MSR Adjustment (4) Scan does work but is very time consuming. Only use it now if we have problems with calibration runs

Operational Problems Fatalities ESD deaths. ~ 0.4 % of on-detector VCSELs died after burn-in (72 hours @ 10 mA and 50C and full QA (~ 30 minutes operation)  rely on redundancy. Maybe lower level damage on more VCSELs will compromise the lifetimes? Slow turn on VCSELs (figure). QA used DC or PSBR data. Real operation involves long gaps between bursts of data. ~ 0.25% of on-detector VCSELs are not usable. Tony Weidberg Pixel Opto November '06

Slow Turn on VCSEL Link 1 has no good value for RX DAC use redundancy Link 0 illustrates intermediate case: can find good RX DAC but lose dynamic range. Tony Weidberg Pixel Opto November '06

Operational Problems Difficulties RX links: Intermediate cases of slow turn on VCSELs can be used but much more care required to set Rxthreshold  slow scan. TX links: some require larger IPIN than normal, may be linked to slow turn on off-detector VCSELs? Tony Weidberg Pixel Opto November '06

Problem Solving Recipes Runs do crash. Often after many minutes in noise occupancy scans because long events suffer more from slow turn on VCSEL problems. Fixes Hard reset ( module CLK/2) and repeat If RXmin>100 reduce VCSEL current If RXmin<100 increase VCSEL current Redo RX threshold scan and RX delay scan. Look at error codes: if they are L1 or BC ID errors  error at start of run  probably slow turn on VCSEL. perform TXscan: scans TX DAC value and sends and returns configuration data (cf RX threshold scan). Increase or decrease IPIN if necessary. (ABCD errors  increase VDD to 4.2V) Have succeeded in simultaneous operation of large number of modules: 672 Barrel 6 in Oxford and 462 barrel modules in SR1 Cosmic run but required a lot of tweaking of parameters. Tony Weidberg Pixel Opto November '06

Tracking Performance TX links RX links. Measure IPIN and check if we see expected decrease in responsivity with radiation damage RX links. Can track performance roughly with RXmin  fig. Better if we could measure I_PIN in array for each channel Tony Weidberg Pixel Opto November '06

Tracking I(p-i-n) Difference I(p-i-n) in a run cf reference run. Mean change in I(p-i-n) versus run number 10% spread due to off-detector VCSEL variation but means show stability over ~ 2 months Tony Weidberg Pixel Opto November '06

RX min correlation with Power Weak correlation Better way: use current measurement in off-detector p-i-n array 12 bits with LSB = 6 mA  ~ O(2%) precision.

Outlook Should take time to debug anomalous channels. Look at signals with optical probe. Easier to debug in SR1 than in pit Can we make DAQ more robust so that single bit errors don’t cause system to crash in calibration runs? Tony Weidberg Pixel Opto November '06