Seminar CARR Fault Coverage Theoretical Estimation 21 February 2005 Center for Advanced Reactor Research Jun-Seok Lee

CARR 2 / 25 Contents I.Introduction II.Literature Review III.Proposed estimation method IV.Discussion V.Summary and Conclusion VI.Further works VII.References

CARR 3 / 25 I. Introduction Background Necessity of safety analysis for reliable digital system. Fault coverage of the digital system is a critical factor for the safety analysis. Fault coverage (C) : the ability to detect faults in a system. Using fault injection techniques for evaluating the fault coverage of a system. Schematic diagram of Digital Plant Protection System Simplified computer for LCL processor LCL Processor

CARR 4 / 25 I. Introduction Experiment Experiment parameters Fault typePermanent fault Program2 out of 4 coincidence logic + Fault detection algorithms Fault modelstuck-at (0, 1) fault Fault Location and Number CPU336 RAM1,050,608 ROM1,048,576 I/O64 Error detection methods Heartbeat-Watchdog Timer, ROM Checksum, RAM data verification, Register write and read, Parity bit, Integration (Heartbeat-Watchdog Timer + ROM Checksum + RAM data verification) Result analysisFault coverage Fault

CARR 5 / 25 I. Introduction Fault coverage of a component (C d,comp ) N injected,comp : the number of injected faults N detected : the number of detected faults. Fault coverage of a system (C d,sys ) λ comp : failure rate of a component (failures/10 6 Hours). Failure rates are calculated using MIL-HDBK-217F.

CARR 6 / 25 I. Introduction Experiment result Integration (25.9%) > RAM data verification (12.2%) > ROM checksum (8.3%) > Heartbeat-Watchdog timer (5.5%) > Register write and read (2.3%) > Parity bit (1.9%)

CARR 7 / 25 I. Introduction Summary & Conclusion of the previous research Possibility of fault coverage evaluation of the DPPS using simulated fault injection method. Fault coverage : Integration > RAM data verification > ROM checksum > Heartbeat- Watchdog timer > Register write and read > Parity bit Defects of the previous research Too long to perform the fault injection experiment. A system model for simulation must be available. Today’s topic Is it possible to reduce the work on fault coverage evaluation using an analytic method?

CARR 8 / 25 II. Literature Review Fault coverage evaluation methods Statistical method (Agrawal) Evaluating a given test set Randomly selected from all faults. Using hyper-geometric distribution ⇒ Obtaining confidence interval with respect to the complete fault set. Empirical method (Huang et al.) Three parameter function for the average fault coverage as a function of test length. Iterative methods for estimating the parameters based on experimental values of fault coverage. Probabilistic method (McCluskey et al.) Modeling fault coverage with test length Deriving formula for expected values of fault coverage. Not yielding accuracy of prediction confidence.

CARR 9 / 25 II. Literature Review McCluskey et al. (1988) Major current issues Selecting the test length Determining the fault coverage Identifying “random pattern resistant” faults Probabilistic model for pseudorandom test pattern generation Advantage : Producing more insight into the relations between network characteristics and test parameters. Disadvantage : Not giving exact fault coverage values of the type that can be obtained from simulation. Related fault coverage to Test length Test inputs Considering stuck-at faults Deriving simplified formula which is applicable to all situations.

CARR 10 / 25 II. Literature Review Fault coverage estimation E(C): Expected fault coverage n f : Number of single stuck-at faults h k : Number of faults of detectability k N : Total number of different input patterns L : Test length ※ Detectability (k) : The number of input patterns which cause the fault to be detected. Example : 3 input AND gate Stuck-at-1 fault on an input lead has k=1 Stuck-at-1 fault on the output lead has k=7 AND i1i2i3out i1 i2 i3 out

CARR 11 / 25 III. Proposed estimation method Defects of the previous literatures Not considering the fault detection algorithm characteristics. Increase in number of unknown parameters using “Detectability” term. Depend on test length and total number of different input patterns. Proposed method Concept The number of used bits or addresses / The number of total bits or addresses Considering Fault detection algorithm Heartbeat-watchdog timer ROM checksum RAM data verification Integration Used bits or addresses in a component CPU, ROM, RAM, and I/O The ratio of the program used to the total Total Program used Error detection program used

CARR 12 / 25 III. Proposed estimation method Program structure To know the self-checking algorithm location in a program. Instruction for components To know the opcode for memory components. Program preset Self-checking Opcode for memory Program structure Instruction

CARR 13 / 25 III. Proposed estimation method Used module consideration For CPU Pick out the module related to the fault detection

CARR 14 / 25 III. Proposed estimation method Assumption A system is made up of CPU, RAM, ROM, and I/O. λ comp : failure rate of a component (failures/10 6 Hours) N injected,comp : the number of injected faults. N detected : the number of detected faults. Permanent stuck-at faults occur in the system. All injected faults are activated. (Percentage of activated faults = 100%) Each component’s fault coverage (C d,comp ) is independent of each other.

CARR 15 / 25 III. Proposed estimation method Heartbeat-watchdog timer CPU Affected modules : Instruction Register (IR), Control Unit (CU), Program Status Word (PSW), Program Counter (PC) Fault affected module ⇒ System infinite loop. RAM Using faulted place ⇒ System infinite loop. ROM Fault in the program-written place ⇒ System infinite loop. I/O Fault at the heartbeat output pin ⇒ Unable to output of the heartbeat signal.

CARR 16 / 25 III. Proposed estimation method ROM checksum CPU Affected modules : Instruction Register, Control Unit, Program Status Word, Data Pointer (Low, High) Fault affected module ⇒ ROM checksum error. RAM Using fault place ⇒ ROM checksum error. ROM Fault in the checksum program ⇒ ROM checksum failure. I/O Stuck-at 0 fault at the fault detection signal output pin ⇒ Unable to output of the fault detection signal.

CARR 17 / 25 III. Proposed estimation method RAM data verification CPU Affected modules : Instruction Register, Control Unit, Accumulator, Program Status Word Fault affected module ⇒ Data verification error. RAM Fault in address for the data verification ⇒ Data verification failure. ROM Fault in the data verification program ⇒ Data verification error I/O Stuck-at 0 fault at the fault detection signal output pin ⇒ Unable to output of the fault detection signal.

CARR 18 / 25 III. Proposed estimation method Integration CPU Affected modules : Instruction Register, Control Unit, Accumulator, Stack Pointer, Data Pointer, Program Status Word, Program Counter RAM Fault in address for the data verification ⇒ Data verification failure. ROM Fault in the checksum program ⇒ ROM checksum failure. I/O Fault at the heartbeat output pin ⇒ Unable to output of the heartbeat signal. Stuck-at 0 fault at the fault detection signal output pin ⇒ Unable to output of the fault detection signal.

CARR 19 / 25 III. Proposed estimation method Component failure rate Parameters B : Number of bits N P : Number of Functional pins Y : Years generic device type has been in production Conditions Environment : Ground benign, 35 ℃ Quality Factor : Class B Package : Dual In-Line Package with Glass Seal CPU RAM ROM I/O The I/O failure rate is critically dependent on temperature and mating/unmating number.

CARR 20 / 25 III. Proposed estimation method Parameters Components Program used bits or addresses Possible casesBitPinYear CPU RAM ROM I/O32--- Heartbeat-watchdog timer ROM checksum RAM data verification Integration CPU RAM51248 ROM I/O1112

CARR 21 / 25 III. Proposed estimation method Result

CARR 22 / 25 IV. Discussion Advantage Very simple expression. ⇒ Easy to use and quick to evaluate. Fault coverage estimation from the system development stage. Possible to consider fault detection characteristics. Disadvantage Application of simplified system. Difference between theory and simulation of CPU. Permanent stuck-at fault only Fault coverage evaluation only. Neglect of “Fault ⇒ Error ⇒ Failure” transition. Unable to evaluate error detection coverage. Unable to classify the undetected error to Not activated case Tolerated case Failure case Fault masking case

CARR 23 / 25 V. Summary and Conclusion Summary Summary of the fault detection coverage evaluation of the DPPS using simulated fault injection experiment Introduction to the fault coverage estimation Statistical method Empirical method Probabilistic method Introduction to the proposed fault coverage estimation Heartbeat-Watchdog timer ROM checksum RAM data verification Integration Conclusion Fault coverage theoretical estimation The number of used bits or addresses / The number of total bits or addresses The proposed fault coverage estimation results RAM, ROM, and I/O : Very close to the simulation results. CPU : Different to the simulation results.

CARR 24 / 25 VI. Further works Supplement of the proposed method Reinforcing theoretical background. Extending to the large system. Coping with various fault types. Considering “Fault ⇒ Error ⇒ Failure” transition.

CARR 25 / 25 VII. References 1.Majumdar A., Sastry, S., “On the distribution of fault coverage and test length in random testing of combinational circuits”, Proceedings of 29th ACM/IEEE Design Automation Conference, 8-12 June 1992, pp Agrawal V. D., “Sampling Techniques for Determining Fault coverage in LSI Circuits”, Journal of Digital Systems, Volume 5, Number 3, pp Huang W. K., M. Lightner and F. Lombardi, “Predicting Fault Coverage for Random Testing of Combinational Circuits”, Proceedings of IEEE International Conference, 1987, pp K. D. Wagner, C. K. Chin and E.J. McCluskey, “Pseudorandom Testing”, IEEE Transactions on Computers, Volume C-36, 1984, pp E. J. McCluskey, S. Makar, S. Mourad, K. D. Wagner, “Probability models for pseudorandom test sequences”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 7, Issue 1, January 1988, pp