EE204 Computer Architecture Processor Data path Control EE204 L11-Datapath Control Hina Anwar Khan 2011

Single Cycle Processor Data path 4 clk Result 1 Result Sh. Left 2 Add Add Single-Cycle Design Read reg. num A Read reg num A Read address Read reg data A Read reg num B Data Memory PC Read address Zero Registers Read data 1 Instruction [31-0] Result Write address Write reg num Instruction Memory Read reg data B Write data Write reg data 1 clk 16 32 clk sign extend EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

The ALU The ALU is stuck right in the middle of everything... It must: Add, Subtract, And, or Or for arithmetic instructions Subtract for a branch on equal Subtract and set for a SLT Add for a memory access 1 A Operation Result + 2 B CarryIn CarryOut BInvert 3 Less Function BInvert Op Carryin Result And 0 00 0 R = A • B Or 0 01 0 R = A Ú B Add 0 10 0 R = A + B Subtract 1 10 1 R = A - B SLT 1 11 1 R = 1 if A < B 0 if A ³ B Always the same: Combine into one signal called “sub” EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Books Table (page 301) EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Setting the ALU controls The instruction Opcode and Function give us the info we need For R-type instructions, Opcode is zero, function code determines ALU controls For I-type instructions, Opcode determines ALU controls New control signal: ALUOp is 00 for memory, 01 for Branch, and 10 for R-type Instruction Opcode ALUOp Funct. Code ALU action ALU control sub op add R-type 10 100000 add 0 10 sub R-type 10 100010 subtract 1 10 and R-type 10 100100 and 0 00 or R-type 10 100101 or 0 01 SLT R-type 10 101010 SLT 1 11 load word LW 00 xxxxxx add 0 10 store word SW 00 xxxxxx add 0 10 branch equal BEQ 01 xxxxxx subtract 1 10 EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Controlling the ALU For ALUOp = 00 or 01, function code is unused AluOp is determined by Opcode - separate logic will generate ALUOp For ALUOp = 00 or 01, function code is unused ALUOp F5 F4 F3 F2 F1 F0 Function ALU Ctrl 00 x x x x x x Add 0 10 01 x x x x x x Sub 1 10 1x x x 0 0 0 0 Add 0 10 1x x x 0 0 1 0 Sub 1 10 1x x x 0 1 0 0 And 0 00 1x x x 0 1 0 1 Or 0 01 1x x x 1 0 1 0 SLT 1 11 ALUOp1 ALUOp0 F0 F3 F1 F2 A0 A1 A2 Since ALUOp can only be 00, 01, or 10, we don’t care what ALUOp2 is when ALUOP1 is 1 A 6-input truth table - use standard minimization techniques EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Decoding the Instruction - Data The instruction holds the key to all of the data signals R-type Opcode RS RT RD ShAmt Function 31-26 25-21 20-16 15-11 10-6 5-0 To ctrl logic Read reg. A Read reg. B Write reg. Not Used To ALU Control Memory, Branch Opcode RS RT Immediate Data 31-26 25-21 20-16 15-0 To ctrl logic Read reg. A Write reg./ Read reg. B Memory address or Branch Offset One problem - Write register number must come from two different places. EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

We can decode the data simply by dividing up the instruction bus Instruction Decoding Opcode: [31-26] 4 Result 1 Result Sh. Left 2 Add Add Op:[31-26] Ctrl Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Read address Rt:[20-16] Data Memory PC Read address Zero Read data 1 Instruction [31-0] 1 Result Write address Instruction Memory Rd: [15-11] Write data 1 Read Reg A: Rs Imm: [15-0] 16 32 Read Reg B: Rt sign extend Write Reg: Either Rd or Rt Immediate Data: [15-0] EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Control Signals ALU Control - A function of: ALUOp 4 Result 1 Load,R-type Result Sh. Left 2 Add BEQ and zero Add PCSrc Op:[31-26] Ctrl MemWrite RegWrite Load Store MemToReg Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A ALUSrc Read address Rt:[20-16] Data Memory Read address Memory PC 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 RegDest Imm: [15-0] R-type 00: Memory 01: Branch 10: R-type 16 sign extend 32 ALU Ctrl MemRead Load FC:[5-0] 6 ALUOp ALU Control - A function of: ALUOp and the function code EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Inside the control oval 00:Mem 01:Branch 10:R-type 0:Reg 1:Imm 1:Mem 0:ALU 0:Rt 1:Rd 1:Branch Reg ALU Mem Reg Mem Mem Instruction Opcode Write Src To Reg Dest Read Write PCSrc ALUOp R-format 000000 1 0 0 1 0 0 0 10 LW 100011 1 1 1 0 1 0 0 00 SW 101011 0 1 x x 0 1 0 00 BEQ 000100 0 0 x x 0 0 1 01 This control logic can be decoded in several ways: Random logic, PLA, PAL Just build hardware that looks for the 4 opcodes For each opcode, assert the appropriate signals Note: BEQ must also check the zero output of the ALU... EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Control Unit Implementation EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Control Signals We must AND BEQ and Zero Ctrl 4 Add Add Data Memory 4 Result 1 Result Sh. Left 2 Add Add PCSrc BEQ Ctrl MemToReg MemRead Op:[31-26] MemWrite ALUOp ALUSrc RegWrite RegDest Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Write Read Read address Rt:[20-16] Data Memory PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 Imm: [15-0] 16 ALU Ctrl sign extend 32 6 FC:[5-0] EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Jumping Ctrl 4 Add Add Data Memory Registers Instruction Memory 32 1 Sh. Left 2 28 Concat. 26 4 4 Result 1 [31-28] Result Sh. Left 2 Add Add Jump PCSrc J:[25-0] BEQ Ctrl MemToReg MemRead Op:[31-26] MemWrite ALUOp ALUSrc RegWrite RegDest Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Write Read Read address Rt:[20-16] Data Memory PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 Imm: [15-0] 16 ALU Ctrl sign extend 32 6 FC:[5-0] EE204 L11-Data Path Control Hina Anwar Khan Spring 2011

Complete Control EE204 L11-Data Path Control Hina Anwar Khan Spring 2011