Logic and Computer Design Fundamentals 1* Logic and Computer Design Fundamentals Chapter 10 Instruction Set Architecture HPCS Lab

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10-1 Computer Architecture Concepts 3 Machine Language binary language defined and stored in memory Assembly Language symbolic language binary opcodes and addresses → symbolic names Architecture whole of the computer instruction set architecture, organization, and hardware HPCS Lab

10-1 Computer Architecture Concepts 4* Instructions Computer usually has a variety of instructions multiple instruction formats instruction format Opcode field – specifies the operation Address field – memory address, address for selecting a register. Mode field – specifies addressing mode Special fields – ex. Positions to shift, immediate operand HPCS Lab

10-1 Computer Architecture Concepts 5* Basic Computer Operation Cycle Fetch the instruction form memory into a control register Decode – determines the operation and the addressing mode Locate the operands used by the instruction Fetch operands from memory Execute the operation in processor registers Store the results in the proper place Go back to step 1 to fetch the next instruction p. 517 HPCS Lab

10-1 Computer Architecture Concepts 6 Register set All registers in the CPU accessible to the programmer Consist Programmer -accessible portion of the register file PC PSR (processor status register) SP (stack pointer) not a part of the register set Not directly accessible Registers in the register file that accessible only to microprograms Instruction register Pipeline registers HPCS Lab

10-2 Operand Addressing Implied address Explicit address 7 Implied address by the opcode Or by an address assigned to one of the other operands No need for a memory or register address field in the instruction Explicit address an operand has an address in the instruction Important factor in defining the instruction The number of operands explicitly addressed The number of such operands HPCS Lab

10-2 Operand Addressing Three-address Instructions X = (A + B)(C + D) 8* Three-address Instructions X = (A + B)(C + D) ADD T1, A, B M[T1] ← M[A] ＋ M[B] ADD T2, C, D M[T2] ← M[C] ＋ M[D] MUL X, T1, T2 M[X] ← M[T1] × M[T2] Use registers ADD R1, A, B R1 ← M[A] ＋ M[B] ADD R2, C, D R2 ← M[C] ＋ M[D] MUL X, R1, R2 M[X] ← R1 × R2 Advantage – short programs Disadvantage – require more bits to specify three addresses HPCS Lab

10-2 Operand Addressing Two-address Instructions X = (A + B)(C + D) 9* Two-address Instructions X = (A + B)(C + D) MOVE T1, A M[T1] ← M[A] ADD T1,B M[T1] ← M[T1] ＋ M[B] MOVE X, C M[X] ← M[C] ADD X,D M[X] ← M[X] ＋ M[D] MUL X,T1 M[X] ← M[X] × M[T1] takes five instructions instead of the three HPCS Lab

10-2 Operand Addressing One-address Instructions X = (A + B)(C + D) 10* One-address Instructions X = (A + B)(C + D) LD A ACC ← M[A] ADD B ACC ← ACC + M[B] ST X M[X] ← ACC LD C ACC ← M[C] ADD D ACC ← ACC + M[D] MUL X ACC ← ACC × M[X] ST X M[X] ←ACC All operation are done between the ACC and a memory. HPCS Lab

10-2 Operand Addressing Zero-address instructions 11* Zero-address instructions all three address must be implied use a stack structure (last in, first out : LIFO) Example : addition ADD TOS ← TOS + TOS-1 X = (A + B)(C + D) PUSH A TOS ← M[A] PUSH B TOS ← M[B] PUSH C TOS ← M[C] PUSH D TOS ← M[D] MUL TOS ← TOS × TOS-1 POP X M[X] ← TOS top of stack HPCS Lab

10-2 Operand Addressing Addressing architectures 12 Addressing architectures memory-to-memory architecture Only control registers All operands come directly from memory The instruction count is low The execution time is potentially high register-to-register architecture (load/store architecture) only one memory address restricts its use to load and store type instructions typical in modern processor instruction count increases memory accesses is reduced HPCS Lab

10-2 Operand Addressing Addressing architectures (cont.) 13 Addressing architectures (cont.) register-to-register architecture : X = (A + B)(C + D) LD R1, A R1 ← M[A] LD R2, B R2 ← M[B] ADD R3, R1, R2 R3 ← R1 + R2 LD R1, C R1 ← M[C] LD R2, D R2 ← M[D] ADD R1, R1, R2 R1 ← R1 + R2 MUL R1, R1, R3 R1 ← R1 × R3 ST X, R1 M[X] ← R1 HPCS Lab

10-2 Operand Addressing Addressing architectures (cont.) 14 Addressing architectures (cont.) register-memory architecture Example ADD R1, A R1 ← R1 + M[A] Prevalent among the current instruction set architectures single accumulator architecture One-address instructions No register file Large number of memory accesses Inefficient HPCS Lab

10-2 Operand Addressing Addressing architectures (cont.) 15 Addressing architectures (cont.) Stack architecture High frequency of memory accesses - since most of the stack is located in memory New architecture in the processor chip Efficient approach postfix notation Reverse Polish Notation (RPN) Example (A + B) × C + (D × E) → A B + C × D E × + HPCS Lab

10-2 Operand Addressing Stack architecture (cont.) 16 (A + B) × C + (D × E) → A B + C × D E × + PUSH A PUSH B ADD PUSH D MUL PUSH E FIGURE 10-1 Graph for Example of Conversion from Infix to RPN p. 523 HPCS Lab

10-2 Operand Addressing Stack architecture (cont.) 17 A B A+B C D × E (A+B) × C + D × E D (A+B) × C FIGURE 10-2 Stack Activity for Execution of Example Stack Program p. 524 HPCS Lab

10-3 Addressing Modes Effective address 18* Effective address To give programming flexibility pointers to memory counters for loop control indexing of data relocation of program To reduce the number of bits Instruction format with a distinct addressing-mode field Opcode Mode Address or operand FIGURE 10-3 Instruction Format with Mode Field p. 525 HPCS Lab

10-3 Addressing Modes Implied Mode Immediate Mode 19* Implied Mode needs no address field the operand is specified implicitly example any instruction that use an accumulator data manipulation in a stack computer Immediate Mode operand field rather than an address field actual operand HPCS Lab

10-3 Addressing Modes Register Modes Register-Indirect Modes 20* Register Modes The address field specifies a processor register The operands are in registers Register-Indirect Modes register contains the memory address of operand use fewer bits to select a register than to specify a memory Autoincrement/Autodecrement mode Similar to the register-indirect mode Incremented or decremented - after its address value is used HPCS Lab

10-3 Addressing Modes Direct Addressing Mode 21* Direct Addressing Mode The address field gives the address of the operand in memory Example one instruction ACC ← M[ADRS] FIGURE 10-4 Example Demonstrating Direct Addressing for a Data Transfer Instruction p. 527 HPCS Lab

10-3 Addressing Modes Direct Addressing Mode (cont.) 22* Direct Addressing Mode (cont.) Branch Instruction ACC ≠ 0 increment ACC = O FIGURE 10-5 Example Demonstrating Direct Addressing in a Branch Instruction p. 528 HPCS Lab

10-3 Addressing Modes Indirect Addressing Mode 23* Indirect Addressing Mode address field - address at which the effective address is stored in memory Relative Addressing Mode added to the content of a specified register (ex. PC) effective address = address part + PC More compact instructions – can be specified with fewer bits HPCS Lab

10-3 Addressing Modes Indexed Addressing Mode 24* Indexed Addressing Mode index register - added to the address part address field - defines the beginning address of the array distance - the index value stored in the register base-register mode – a specialized variation of the index mode base register - added to the address part index register - hold an index number that is relative to the address field HPCS Lab

10-3 Addressing Modes Summary of Addressing Modes load to ACC 25* load to ACC Summary of Addressing Modes In the immediate mode the operand 500 is loaded into the ACC In the relative mode effective address 500+252=752 operand = 600 PC=PC+2 In the indirect mode effective address = 800 operand = 300 In the index mode effective address 500+400=900 In the register mode In the register-indirect mode effective address = R1 operand = 700 In the direct mode effective address = 500 operand to be loaded into ACC = 800 FIGURE 10-6 Numerical Example for Addressing Modes p. 530 HPCS Lab

10-3 Addressing Modes Summary of Addressing Modes (cont.) 26* Summary of Addressing Modes (cont.) p. 531 Some compilers or assemblers designate with @ LDA @ADRS TABLE 10-1 Symbolic Convention for Addressing Modes HPCS Lab

10-4 Instruction Set Architectures 27* Instruction Set Architectures Two major types of instruction set architectures Complex Instruction Set Computers (CISCs) hardware support for high-level language operations compact programs Reduced Instruction Set Computers (RISCs) Simple instructions flexibility higher throughput faster execution HPCS Lab

10-4 Instruction Set Architectures 28* RISC architecture Memory accesses - restricted to load and store data manipulation - register to register Addressing modes - limited in number Instruction formats - all of the same length Instructions perform elementary operations Goal – high throughput and fast execution memory accesses – avoided large register file fixed instruction length, limited addressing modes Elementary operations hardwired control unit pipeline design HPCS Lab

10-4 Instruction Set Architectures 29* CISC architecture Memory access – directly available Addressing modes – substantial in number Instruction formats – different lengths Instruction – both elementary and complex operations Goal Support closely operations used in high-level language compact programs and conserve memory reduction in the number of instruction fetches microprogrammed control - instruction complexity, variability of the instruction formats HPCS Lab

10-5 Data Transfer Instructions 30* move data from one place to another without changing typical data transfer instruction TABLE 10-2 Typical Data Transfer Instructions p. 533 HPCS Lab

10-5 Data Transfer Instructions 31* Stack Instructions Push Pop Nothing is really physically pushed or popped Stack pointer (SP) – always points to the item at the top Push, Pop - implemented by decrementing or incrementing the stack pointer HPCS Lab

10-5 Data Transfer Instructions 32* Stack Instructions (cont.) POP operation R1 ← M[SP] SP ← SP + 1 Not physically removed PUSH operation SP ← SP - 1 M[SP] ← R1 C FIGURE 10-7 Memory Stack p. 534 HPCS Lab

10-5 Data Transfer Instructions 33* Independent versus Memory-Mapped I/O I/O instruction - Between processor registers and I/O devices Port – a register with I/O lines attached to the device Port address assign – two ways independent I/O system – address ranges are independent Isolates memory and I/O selection Isolated I/O configuration Memory-mapped I/O assigns a subrange of the memory address for I/O port Same instructions are used both memory and I/O data HPCS Lab

10-6 Data Manipulation Instructions 34 Three basic types Arithmetic instructions Logical and bit manipulation instructions Shift instructions Processed by executing a sequence of microinstructions Fetch the instruction Bring the operands from appropriate processor registers Store the result in the specified location HPCS Lab

10-6 Data Manipulation Instructions 35* Arithmetic Instructions Four basic arithmetic instruction : addition, subtraction, multiplication, division 0000 : 1010 Carry/borrow from the previous computation B – A ↕ A - B TABLE 10-3 Typical Arithmetic Instructions p. 537 HPCS Lab 2’s complement of signed number

10-6 Data Manipulation Instructions 36* Logical and Bit Manipulation Instructions replaced by 1’s bit set instruction mask, bit clear instruction bit complement instruction TABLE 10-4 Typical Logical and Bit Manipulation Instructions p. 538 HPCS Lab

10-6 Data Manipulation Instructions 37* Shift Instructions logical shifts, arithmetic shifts, rotate-type shifts p. 539 TABLE 10-5 Typical Shift Instructions HPCS Lab

10-7 Floating-point Computations 38 Floating-point number sign and fraction(mantissa) exponent – the position of the radix point Example –binary number 1001.10 only the fraction and the exponent are physically represented Radix 2 for the exponent Normalized If the most significant digit is nonzero 0.350 normalized 0.0035 not normalized provide the maximum possible precision Zero – can’t be normalized; usually all 0’s 01001010 000100 Fraction Exponent + (0.1001010)2 × 2+4 HPCS Lab

10-7 Floating-point Computations 39 Arithmetic Operation Adding and subtracting requires that the radix points be aligned done by shifting one fraction correspondingly adjusting exponent until the exponent is equal to the other exponent Adding Subtracting .5372400 × 102 .1580000 × 10-1 + .0001580 × 102 .5373980 × 102 .56780 × 105 - .56430 × 105 .00350 × 105 .35000 × 103 Not normalized HPCS Lab

10-7 Floating-point Computations 40 Biased Exponent bias – an excess number added to the exponent the sign is removed example Consider the range of exponents –99 ~ +99 Excess 99 e = E + 99 , E is the actual exponent E = -99, e = -99 + 99 = 0 E = +99, e = 99 + 99 = 198 advantage Simpler to compare the relative magnitude Zero is the smallest possible exponent HPCS Lab

10-7 Floating-point Computations 41* Standard Operand Format Two standard formats Single precision data type – 32bits Double precision data type – 64bits sign for the fraction fraction FIGURE 10-8 IEEE Floating-Point Operand Format exponent f Field Significand Decimal Equivalent 100 … 0 1.100 … 0 1.50 010 … 0 1.010 … 0 1.25 000 … 0 1.000 … 0* 1.00* p. 543 * Assuming the exponent is not equal to 00 … 0. HPCS Lab

10-7 Floating-point Computations 42* Evaluating biased exponents (-1)s 2e -127×(1.f ) TABLE 10-6 Evaluating Biased Exponents p. 544 HPCS Lab

10-7 Floating-point Computations 43 When e ＝ 255 and f ＝ 0 The number represents plus or minus infinity Sign is determined from the sign bit s. When e ＝ 255 and f ≠ 0 Not a number, or NaN When e = 0 and f = 0 The number of denotes plus or minus zero When e = 0 and f ≠ 0 The number is said to be denormalized HPCS Lab

10-8 Program Control Instructions 44 In-line sequencing Next instruction is fetched from the next adjacent location PC ← PC + 1 Address from other source Load PC with a new address coming from current instruction, stack, and etc. Branch Conditional Branch Subroutines etc HPCS Lab

10-8 Program Control Instructions 45* Typical Program Control Instructions TABLE 10-7 Typical Program Control Instructions p. 545 HPCS Lab

10-8 Program Control Instructions 46* Conditional Branch Instructions Depending on the value of stored bit in the PSR If condition = true, control transferred to the effective address If condition = false, the next instruction Branch Status Bit Zero Carry Leftmost Overflow TABLE 10-8 Conditional Branch Instructions Relating to Status Bits in the PSR p. 547 HPCS Lab

10-8 Program Control Instructions 47 Conditional Branch Instructions (cont.) For unsigned numbers Subtracting A-B and checking the C and Z status bits TABLE 10-9 Conditional Branch Instructions for Unsigned Numbers p. 547 HPCS Lab

10-8 Program Control Instructions 48 Conditional Branch Instructions (cont.) For signed numbers The status bits N, V and Z after a subtraction A-B TABLE 10-10 Conditional Branch Instruction for Signed Numbers p. 548 HPCS Lab

10-8 Program Control Instructions 49* Procedure Call and Return Instructions Procedure A self-contained sequence of instructions A branch is made to the beginning to start executing After it has been executed, a branch is made to return Is also called a subroutine Call Procedure stores the value of the PC – return address loads the address of the first instruction in the procedure Return to the calling procedure PC ← stored address by the call procedure instruction - return address HPCS Lab

10-8 Program Control Instructions 50* Procedure Call and Return Instructions (cont.) temporary locations for storing the return address different computers use different locations fixed location in memory, processor register, memory stack Stack procedure call instruction SP ← SP – 1 decrement stack pointer M[SP] ← PC store return address on stack PC ← effective address transfer control to procedure return instruction PC ← M[SP] transfer return address to PC SP ← SP + 1 increment stack pointer All return addresses are automatically stored by hardware No need to concerned about managing the return address HPCS Lab

10-9 Program Interrupt Program Interrupt 51* Program Interrupt used to handle a variety of situations that require a departure from the normal program sequence transfers control from a program to another service program Control returns after the service program is executed differs from a call procedure Usually initiated at an unpredictable point by external or internal signal The address of the service program is determined by a hardware procedure It is necessary to store information that defines all or part of the contents of the register set HPCS Lab

10-9 Program Interrupt 52* The computer must return to exactly the same state that it was in before the interrupt occurred The PSR can specify what interrupts are allowed to occur Whether the computer is operating in user of system mode User mode – user program system mode – operating system Most computers will not respond to an interrupt until the instruction in the process of being executed is executed HPCS Lab

10-9 Program Interrupt Types of Interrupts External interrupts 53* Types of Interrupts External interrupts I/O devices, timing devices, circuit monitoring, any other external source Internal interrupts (traps) The illegal or erroneous use of an instruction or data Software interrupts Initiated by executing an instruction A special call instruction that behaves like an interrupt Associated with a system call instruction Exception which may apply only to internal interrupts or to all interrupts HPCS Lab

10-9 Program Interrupt Processing External Interrupts 54* To ensure that no information is lost After the execution of the current instruction is completed If the state of the processor warrants it Processing External Interrupts Allows the programmer to decide whether to use the interrupt facility ENI – enable interrupt DNI – disable interrupt FIGURE 10-9 Example of External Interrupt Configuration HPCS Lab

10-9 Program Interrupt Processing External Interrupts (cont.) 55* Processing External Interrupts (cont.) implement the interrupt SP ← SP – 1 decrement stack pointer M[SP] ← PC store return address on stack M[SP] ← PSR store processor status word on stack EI ← 0 reset enable-interrupt flip-flop INTACK ← 1 enable interrupt acknowledge PC ← IVAD transfer interrupt vector address to PC go to fetch phase return from interrupt the stack is popped return address is transferred to the PC HPCS Lab