Exam-like questions
Write the machine code for the following assembly code L0:add $0, $1, $2 sub $3, $3, $1 lw $3, 12($0) beq $3, $0, L1 add $3, $3, $1 sw $3, 0($3) L1:beq $0, $0, L0 Opcode -- add: 000000, sub: 000000, lw: 100011, sw: 101011, beq: 000100 Funct -- add: 100000, sub: 100010 000000 00001 00010 00000 00000 100000 000000 00011 00001 00011 00000 100010 100011 00000 00011 0000000000001100 000100 00011 00000 0000000000001000 000000 00011 00001 00011 00000 100000 101011 00011 00011 0000000000000000 000100 00000 00000 1111111111100100 Remember, labels are relative to PC+4 in a branch instruction
(a). Watch the ordering on questions like this
The sequence generated is 0,2,2,2,2,2,…
Problem (d).
Problem (d). Our datapath can do this, and we can fit it into an instruction. Putting this into a pseudo-instruction can be done in 2 instructions. (address calculation, then load)
Sample written #1 Design a circuit that has two inputs, clk and X, and produces one output O. X may change every clock cycle, and the change happens at the falling edge. The circuit samples the input at every rising edge of the clock. If the input is 1, consider as read a 1, else read a 0. O is 1 (for one clock cycle, from positive edge to positive edge) if the last three bits read are 110, with 0 as the most recent bit. Draw the state diagram. Close to an arc, show X=1 or X=0 to indicate whether the change of state happens when X=1 or when X=0. Draw the next-state table, and derive the functions for D1 and D0 from the table Simplify functions D1 and D0 Derive the output function O. Draw the circuit See HW6 part 2 for most of this (except drawing circuit)
Assume that How fast is Memory access: 200ps ALU and adders: 100 ps What should the clock be set to, assuming the following timings: Assume that Memory access: 200ps ALU and adders: 100 ps Register file read: 50ps Register file write: 50ps (the clk-to-q delay) PC update: 10ps (the clk-to-q delay) The setup time of DFFs: 10ps Other parts do not have delay What is the critical path? How fast is An R-type instruction? A jmemi instruction?