G. RizzoSVT - SuperB Workshop – Paris 16 Feb SVT Plans for TDR Activities since Elba Meeting Plans for TDR preparation Giuliana Rizzo Universita’ & INFN Pisa

G. RizzoSVT - SuperB Workshop – Paris 16 Feb SVT for SuperB Striplets option: mature technology, not so robust against background. Marginal with background rate higher than ~ 5 MHz/cm 2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option new & challenging technology: can provide the required thickness existing devices are too slow Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um 2 Hybrid Pixel Option: tends to be too thick + large pitch Alice hybrid pixel module ~ 1% X0, pitch 50x150 um2 Possible material/pitch reduction with the latest technology improvements. Viable option but requires some R&D The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large background and needs to be extremely thin: > 5MHz/cm2, 1MRad/yr, ~ 0.5%X0

G. RizzoSVT - SuperB Workshop – Paris 16 Feb During the summer focus on the preparation of the September testbeam  conclusion of the SLIM5 3 years project. –Devices under test: first prototypes for SVT Layer 0 CMOS MAPS matrix (4096 pixels, 50x50  m pitch) with on chip sparsified readout architecture. Striplets modules (200 um thick) with FSSR2 chips. –Many different parts built by the group to have a facility also for future tests on beam: Reference telescope with double sided strip detectors Prototype hybrids with FSSR2 readout chips for strip/striplets Support table with xyz, theta motion New DAQ system for data push architecture (FSSR2 and MAPS chips) New Associative Memories board with LV1 trigger capability SVT (SLIM5) Beam Test CERN

G. RizzoSVT - SuperB Workshop – Paris 16 Feb R&D on CMOS MAPS continue The testbeam was a success! –First confirmation with beams of good performance of the MAPS device –Results on next talks (Bettarini, Bomben, Villa) Improvements implemented in 2 new MAPS chips already in production (smaller cell, improved sensor geometry, digital cross talk reduction) Present R&D on DNW MAPS very encouraging Next step: demonstrate the ability to build a working detector with CMOS MAPS. –Scalability to larger matrix (Area ~1 cm2): Main issues power distribution, output rate. efficiency of the readout architecture Plan to build a prototype multichip MAPS module suitable for application in Layer 0. –Testbeam in Activity funded by INFN. Institutions: Bologna, Milano, Pavia/Bergamo, Pisa, Roma III, Torino, Trieste.

G. RizzoSVT - SuperB Workshop – Paris 16 Feb R&D on CMOS MAPS continue The testbeam was a success! –First confirmation with beams of good performance of the MAPS device –Results on next talks (Bettarini, Bomben, Villa) Improvements implemented in 2 new MAPS chips already in production (smaller cell, improved sensor geometry, digital cross talk reduction) Present R&D on DNW MAPS very encouraging Next step: demonstrate the ability to build a working detector with CMOS MAPS. –Scalability to larger matrix (Area ~1 cm2): Main issues power distribution, output rate. efficiency of the readout architecture Plan to build a prototype multichip MAPS module suitable for application in Layer 0. –Testbeam in Activity funded by INFN. Institutions: Bologna, Milano, Pavia/Bergamo, Pisa, Roma III, Torino, Trieste.

G. RizzoSVT - SuperB Workshop – Paris 16 Feb CMOS MAPS module for Layer0 Bonding and module assembly (PI) Thermoidraulic lab test. (PI) DAQ for pixel module (BO) Radiation damage studies on MAPS (PV/BG-PI) The prototype module will be a smaller version of the final Layer 0 module. Specs similar to the final one: readout speed, total material budget. –2-3 MAPS chips ~ 128x128 pixels, evolution of the APSEL4D just tested on beam: architecture data push with sparsificaition on chip, data driven, (ST Microlelectronics 130 nm) PV/BG, PI, BO, Roma III –Al multilayer bus for interconnection (similar to the ALICE pixel bus) (MI) –HDI collects data from FE chips and will need some “intelligence” implemented on FPGA (  ASIC in future rad. Hardness is an issue). FE chips are data push but so we need local buffer to store data waiting for LV1 trigger from. Similar approach for HDI with FSSR2 chips for striplets and external layers. (MI, TS) –Develop light support in carbon fiber with integrated microchannel for cooling. (PI) –Alternative support & cooling for pixels under evaluation (MI-TO). All the parts realized in 2009, Assembly and test starting by the end of Testbeam in 2010.

G. RizzoSVT - SuperB Workshop – Paris 16 Feb Activities now more focused on TDR preparation (end of 2010) Some R&D still needed for Layer 0: Plan to build a multichip CMOS MAPS prototype module with specs close to the SuperB Layer0 requirements  Testbeam in –All the module components could be the same for a Layer0 module based on Hybrid Pixels. Hybrid Pixel: more emphasis now on this option: it could become the baseline Layer0 option for the TDR in case MAPS are not considered mature enough by that time. –Need to demonstrate by 2010 that reduction in the front-end pitch to 50x50  m 2 and in the total material budget is possible to meet Layer0 requirements. Striplets: continue to evaluate the use of FSSR2 readout chip and light interconnections from sensor to front-end SVT Activities for TDR (I) Activity funded by INFN. Institutions: Bologna, Milano, Pavia/Bergamo, Pisa, Roma III, Torino, Trieste.

G. RizzoSVT - SuperB Workshop – Paris 16 Feb Background Simulation: This set the scale for requirements on Layer0 and the inner SVT Layers. External Layers Design Technology is not an issue Need to optimize the geometry with Fast Simulation (D. Brown’s talk) Need to evaluate the best front-end chip for strip modules among the ones “on the market” ( FSSR2…) Off Detector electronics and DAQ Development (M. Citterio, M. Villa’s talk) Mechanics: Beam-pipe design Light support and cooling for Layer0 modules (F.Bosi’s talk) Module design for the external Layers Design the full SVT support structure (want to have the Layer0 easily accessible for replacement). Important interplay with IR design. SVT Activities for TDR (II) A significant amount of work is needed for the TDR and not all listed activities are well covered.

G. RizzoSVT - SuperB Workshop – Paris 16 Feb New Projects on Vertical Scale Integration (VSI) Vertical scale integration process allows to have a chip comprised of 2 or more layers of active semiconductor devices that have been thinned, bonded and interconnected to form a “monolithic” circuit –This can overcome some of the limitation of the present MAPS devices VSI process are now available for R&D with reasonable costs. VIPIX Project – Vertically Integrated PIXel – INFN ( ) Institutes : BO, PI, PG, PV/BG, RM3, TN(PD), TO, TS ~ 17 FTE Goal: Develop a light pixel detector system based on Vertical Scale Integration technology. Using Charterd-Tezzaron 130 nm process plan to build –CMOS MAPS in VSI (2 layers), Front-end chip for hybrid pixel in VSI (2 layers) –High resistivity pixel sensor connected to front-end chip by bump bonding 1 st step PRIN2007 Project – Italian Ministry for Education and Research ( ) Goal: Vertical Scale Integration between high resistivity pixel sensor and front-end chip Thin pixel detectors realized in VSI would be the best option for the SVT Layer0, of course the technology is not mature today to be proposed in the SuperB TDR but technological advances are fast and evolving in a time scale of 1-2 years…

G. RizzoSVT - SuperB Workshop – Paris 16 Feb backup

G. RizzoSVT - SuperB Workshop – Paris 16 Feb SVT (SLIM5) Beam Test CERN Successfully tested two options for Layer0: CMOS MAPS matrix with fast readout architecture (4096 pixels, 50x50  m pitch, in-pixel sparsification and timestamp) –Hit efficiency up to 92% (room for improvement with sensor design optimized) –Good uniformity across the matrix. –Intrisinc resolution ~ 14  m compatible with 50  m pitch and digital readout. Thin (200  m) striplets module with FSSR2 readout chips (not optimized to read the n-side) –S/N=25 (p-side) First demostration of LVL1 capability with silicon tracker information sent to Associative Memories MAPS Hit Efficiency vs threshold MAPS resolution vs threshold

G. RizzoSVT - SuperB Workshop – Paris 16 Feb Beam test Beam test 3-16 September CERN (T9). Main goals: –DNW MAPS matrix resolution & efficiency –Thin (200  m) striplets module with FSSR2 readout chips –Demostrate LVL1 capability with tracker information sent to Associative Memories Testbeam analysis ongoing: first encouraging results presented at the last SuperB Det Meeting by Nicola Neri. beam T-1,2,3,4 :reference telescope modules S1 S2 S3 T-2,1 T-4,3 Striplets-1 Striplets-2 MAPS-1 MAPS-2

G. RizzoSVT - SuperB Workshop – Paris 16 Feb Low mass support & cooling for Layer0 pixel modules Developed a module support structures with cooling microchannel integrated in the Carbon Fiber/Ceramics support 0.35 % X 0 –The total thickness of the support structure + cooling fluid + peek + glue is: 0.35 % X 0 –Consistent with the requirements First thermoidraulic measurements in good agreement with simulation and within specs. Cooling system based on microchannels can be a viable solution to the thermal and structural problems of the Layer0 detector, Simulated module Carbon Fiber Module T FLUID 9.5 °C Heater Pw2 W/cm 2 Capacity0.7 Kg/min T _IN 41.1 °C T _OUT 43 °C P _IN 2.6 bar 12.8 mm 3 mm Simulation: T_IN = 37 °C (variation of several degrees possible due to uncertainty on thermal conductivity of kapton and glue) Details of Ceramic and Carbon Fiber support Measurements Temp. sensor 2 W/cm2