An Introduction to V.H.D.L.

Need of a Compiler… main( ) { int x=10,y=20,z; z = x + y ; printf ( “ %d “, z ); getch( ) ; } What’s That ? Give me only Oh ! That’s ENGLISH-LIKE !! Turbo C- Compiler That’s delicious !!

Strengths & Limitations of C Strengths… C is an extremely powerful Language. In fact even JAVA Compiler has been written Using C Language. Limitations… C is a sequential language & the statements are executed in the order in which they are written. But Electronic Hardware is CONCURRENT in Nature, which means it functions on the occurrence of EVENTS. eg. In Asynchronous Counter when LSB F/F outputs a 1  0 then middle F/F changes state and so on…till MSB F/F. C LANGUAGE cannot represent the CONCURRENT Nature of Electronic Hardware EFFICIENTLY. Thus there is a need of a Special language which can efficiently represent the behavior of Electronics Hardware.

VHDL VHDL = V + H.D.L. Hardware Description Language V.H.S.I.C. means V ery H igh S peed I ntegrated C ircuit Thus….. V.H.D.L. = Very High Speed Integrated Circuit Hardware Description Language

Things common to all Languages… Basic Program Constructs. Grammar ( called as SYNTAX ). Variables & ways of declaring them. Data Types ( What values the variables can hold ) Language Compiler ( To convert English-Like Program into Machine-Language ) Thus Learning VHDL is nothing but learning NEWer ways of doing the above things.

main( ) { int x=10,y=20,z; z = x + y ; printf ( “ %d “, z ); getch( ) ; } C-Compiler ( Software ) Syntax Check Generates.obj File ie. Program into machine language ( ….) Processor ( Hardware ) The ALU Then Adds the 2 nos. 10 & 20 and Generates the result 30. VHDL Program For Half-Adder, MUX, Counter, µ Controller SYNTHESIS TOOL ( XILINX Software ) Syntax Check Converts VHDL Code Program into a GATE- LEVEL NETLIST ( ….) CPLD / FPGA ( Programmable H/W ) The above device then operates as the desired Digital Circuit ( Half-Adder, MUX, Counter, Or even a MicroController ) Programming Instructions On your PC

Always remember…. VHDL is a Hardware Description Language. Hence its primary usage is to describe DIGITAL HARDWARE. Digital Circuits are ultimately made up of LOGIC GATES. VHDL Language has Keywords such as AND,OR,NOT,XOR,XNOR which can be used to describe LOGIC GATES. Hence VHDL can efficiently represent a DIGITAL SYSTEM. Representing a certain DIGITAL SYSTEM along with its Behavior is called as ‘MODELING’.

D Flip-Flop DADA DBDB QBQB QAQA

A VHDL Program may consist of…. ENTITY Declaration. ARCHITECTURE Body. Configuration Declaration. Package * Body. * Package Declaration. All Declarations are called P.D.U’s ( Primary Design Units ) All Body’s are called S.D.U’s ( Secondary Design Units ) compulsory optional

Syntax For Entity Declaration ENTITY entity_name IS PORT ( signalname_1 : [ MODE ] [ DATATYPE ] ; signalname_2 : [ MODE ] [ DATATYPE ] ; signalname_3 : [ MODE ] [ DATATYPE ] ;.. signalname_n : [ MODE ] [ DATATYPE ] ) ; END entity_name ; NO Semi-colon after Last Signal IN / OUT / INOUT 1) BIT ( 2-Valued Logic ) 2) STD_LOGIC ( 9-Valued LOGIC ) --Preferred

Example of ED For an AND Gate and_gate A B Y ENTITY and_gate IS PORT ( A : IN STD_LOGIC ; B : IN STD_LOGIC ; Y : OUT STD_LOGIC ) ; END and_gate ;

Syntax For ARCHITECTURE BODY ARCHITECTURE arch_name OF entity_name IS Local variables / Global Variables / Constants / …..Don’t write anything if not needed BEGIN END arch_name ; --Your Programming LOGIC Here you Mention “ The Logical Relationship between your INPUTS & OUTPUTS”

Example of AB For AND Gate ARCHITECTURE andgate_arch OF and_gate IS BEGIN Y < = A and B ; END arch_name ;

The Complete VHDL Program For AND Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY and_gate IS PORT ( A : IN STD_LOGIC ; B : IN STD_LOGIC ; Y : OUT STD_LOGIC ) ; END and_gate ; ARCHITECTURE andgate_arch OF and_gate IS BEGIN Y < = A and B ; END arch_name ;

VHDL Program For 4:1 MUX 4:1 MUX I0 I1 Y I2 I3 s1s0

The Complete VHDL Program For 4:1 MUX entity mux41 is Port ( I : in std_logic_vector(0 to 3); s : in std_logic_vector(1 downto 0); Y : out std_logic ); end mux41; architecture mux41_arch of mux41 is begin Y <= I(0) when s="00" else I(1) when s="01" else I(2) when s="10" else I(3) ; end mux41_arch;

VHDL Program For 3-Bit Up-DOWN COUNTER ENTITY counter3bit IS PORT ( clk : IN std_logic; reset : IN std_logic; mode : in std_logic; Q : OUT std_logic_vector( 2 downto 0 ) ) ; END counter3bit ; Entity Declaration

Architecture Body architecture Behavioral of updncounter is SIGNAL tempcount : STD_LOGIC_VECTOR(2 downto 0); begin PROCESS( clk, reset, mode ) BEGIN IF reset='1' THEN tempcount <= "000" ; ELSIF clk'event AND clk = '0' THEN IF mode = '1' THEN tempcount <= tempcount + 1 ; ELSE tempcount <= tempcount - 1 ; END IF; END IF; END PROCESS; Q <= tempcount; end Behavioral; Temporary Signal

STRUCTURAL Modeling Style FULL ADDER a b cin cout sum

STRUCTURAL Modeling Style… a b cin cout sum x1 c1 add1 x2 s1 x1 c1 add2 x2 s1 carry1 sum1 carry2

entity adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; cout : out std_logic ); end adder ; architecture adder_arch is component add is port ( x1,x2 : in std_logic; s1,c1 : out std_logic); end component; SIGNAL sum1,carry1,carry2 : std_logic ; begin add1 : add port map (x1=>a,x2=>b,c1=>carry1,s1=>sum1); add2 : add port map (x1=>sum1,x2=>c,c1=>carry2,s1=>sum); cout<=carry1 OR carry2; end adder_arch;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity add is port(x1,x2 : in std_logic; s1,c1 : out std_logic); end add; architecture add_struct of add is begin s1<= x1 xor x2; c1<=x1 and x2; end add_struct;