INF3430 / 4431 Synthesis and the Integrated Logic Analyzer (ILA) (WORK IN PROGRESS)

INF3430 / INF4430Synthesis and the Integrated Logic Analyzer - Outline2 Outline RTL synthesis Constraints Pipelining Synthesis for FPGA Integrated Logic Analyzer (ILA)

RTL/”Behavioral” synthesis RTL (Register Transfer Level) synthesis –Generates a netlist (or boolean functions) of a VHDL-description of registers, state machines, and combinatorial logic –All clocks and registers in the design are visible Behavioral synthesis –Based on algorithms and architecture –Does not need specific clocks or registers –Can use high level languages like System C INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis3

RTL synthesis A number of different features of the circuit needs to be known before making an RTL description: –Inputs and outputs –All registers –All clocks –Number of states in a state machine RTL synthesis tools can not minimize the number of states –We can affect the result of the synthesis by using constraints An example is to choose the state coding for a state machine –Minimum/maximum requirements An example is the minimum clock frequency of the system INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis4

Synthesizable code IEEE defines a subset of VHDL that can be synthesized –Previously presented code is synthesizable (except testbenches) Non-synthesizable functions in VHDL are typically connected to absolute time or file I/O: –Code with the after, delay or wait for keywords –Use of exact timing –Any file I/O gives an error message –Array dimensions must be known before synthesis Generic parameters must have default values –Do not set the same signal in multiple processes (except tristate- buffers) INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis5

Unwanted latches To only get combinatorial logic: –Add else in if then else sentences –Add when others in case sentences –And/or use default values INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis6

Example of latch generation I Synthesis of the process p0 results in a transparent latch because we have no else in the if sentence Synthesis of the process p1 results in a purely combinatorial circuit (mux between A and ‘0’) INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis7

Example of latch generation II Synthesis of the process p2 results in a latch because we have no when others or default values in the process Synthesis of the process p3 results in a purely combinatorial circuit because we have when others or set default in the process P3 and P4 are equivalent INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis8 p3: p2: p4:

Unwanted hazard Feedback loops can give hazards (glitches) due to different delays, and are a bad way of generating latches INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis9

Flip-flops Use the functions rising_edge or falling_edge to make edge triggered flip-flops It is important to use else on the same level as the edge detection INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis10

Use of variables INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis11

RTL synthesis conclusion INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – RTL synthesis12

Synthesis constraints Synthesis / place and route results can be affected by using constraints Types of constraints –Optimization goals Speed vs area vs low power –Timing Clock frequency Clock to output delay Input setup time The low scale of circuits makes the routing the main contribution to delays due to resistance and capacitance –It is important that synthesis tools use physical effects into consideration –It is traditionally the Place and Route tools that use timing the constraints INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints13

Register-register delay I INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints14 clk Register-register delay

Register-register delay II INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints15 clk Register-register delay rising edge to falling edge

Register-register delay III INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints16 clk1 Register-register delay clk1 rising to clk2 rising clk2

Clock to output delay INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints17 clk out buffer (different slew-rate options) d d q Clock to output clk q out

Input to clock delay INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints18 inp buffer (kontrollerbart Input delay ??) inp d Input to clock clk q q d

Global constraints in Xilinx Vivado INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints19

RTL synthesis and technology Important questions to ask when doing RTL synthesis and choosing technology –How does the circuit handle reset? –How are clocks distributed and what resources are available? –What are the register requirements? –How does the circuit handle tri-state? –What requirements do we have for throughput/latency? The answers to these questions affect our RTL code! INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints20

Using meta comments All flip-flops are reset asynchronously at power-on in Xilinx FPGAs –Use of asynchronous reset can make the design slower How can we describe the flip-flops in VHDL without including the reset signal? Meta comments can be used to guide the synthesis –A meta comment is written as a normal comment. It is ignored by simulation, but the synthesis tool uses it –Can be compared to pre-processor directives in C The synthesis standard IEEE defines two meta comments --rtl_synthesis off / --rtl_synthesis on to control what is synthesized Vivado uses -- synthesis translate_off / -- synthesis translate_on INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints21

Example entity Goal: –Make a flip flop that we can reset asynchronously to 0 by controlling the reset signal during RTL simulation –We wish to synthesize this without a reset input Solution: –Add a meta comment to disable synthesis INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints22

Example architecture INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints23

Simulation only code This can also be used to add simulation only code Can be used to make reports in RTL that is only used in simulation INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints24

Other meta comments Vivado has a range of other meta comments, described in document UG901 –FSM_ENCODING – sets FSM encoding in code –USE_DSP48 – enable/disable usage of DSP elements –RAM_STYLE – sets inferred RAM type (reg / dist / bram) –ROM_STYLE – sets inferred ROM type (dist / bram) –ASYNC_REG – declares an asynchronous input D pin –MAX_FANOUT – sets fanout for registers and signals –KEEP – disable optimizations on signal –MARK_DEBUG – mark a signal for later debug with ILA INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Constraints25

Multiplexers / tristate Some FPGA families contain internal tri-state buffers. These can be used as an alternative to multiplexers. Use of tri-state buffers in this way is very technology dependent –This will not be possible on ACTEL FPGAs as these do not have internal tri-state buffers. –Different fan-out is one of the reasons for these differences INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Pipelining26

Fanout and capacitive load I INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Pipelining27 clk d RL C RL C Rin

Fanout and capacitive load II An output is connected to many inputs –Limitations on the number of inputs that can be driven due to the additional resistance from Rin. CMOS has a high Rin, and we therefore get a high fanout –The delay is mostly increased due to increased capacitive load It is important to control placement and fanout –Control of fanout Synthesis constraint – max fanout Synthesis duplication of registers to decrease fanout Synthesis addition of buffers to decrease fanout INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Pipelining28

Fanout A fanout of 16 means that an output can drive 16 inputs without degradation of the signal The example to the right will not work as it drives too many inputs Solution: –Split enable into two groups –Let the synthesis tool add more buffers automatically INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Pipelining29

Throughput vs latency Pipelining is often used in FPGA to achieve a high clock frequency (high throughput) –This is a consequence of narrow logical blocks Pipelining is splitting a logical operation into smaller parts, and adding registers in between This adds a latency from input to output INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Pipelining30

State machine / timing INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Synthesis for FPGA31

Debouncing Goal –A single press of a button should give a signal with the duration of a single clock cycle, «one-shot» Problem –The button is never released quick enough One press can be read as several –Bounce False pulses INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Synthesis for FPGA32

Debouncing example INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Synthesis for FPGA33 Clk btn Synchronized btn One-shot btn

Integrated Logic Analyzer Added in Vivado during the design of a circuit Used as a logic analyzer to see how the hardware circuit acts during testing User-selectable triggers, data width and data depth Can debug simple signals or bus interfaces like AXI Video from Xilinx: Programming and Debugging Design in Hardware INF3430 / INF4431Synthesis and the Integrated Logic Analyzer – Integrated Logic Analyzer (ILA)34