What is CRKIT Framework ? Baseband Processor :  FPGA-based off-the-shelf board  Control up to 4 full-duplex wideband radios  FPGA-based System-on-Chip (FSoC) implementation Wideband Radio (WDR) Module :  Wideband : tunable range 300MHz to 7.5GHz  25MHz bandwidth  50Msps 12-bit ADC, 200Msps 12-bit DAC  50us switch between frequencies Actual CogRadio with enclosure, 2 WDRs CRKIT baseband with 4 stacked radios CRKIT HW Platform SW Platform ORBIT Integration Wideband Radio Flexible Baseband PHY Layer Exp. Exp. Scalability EmbeddedHOST FPGA- SoC Comm. APPs Radio APIs OMF Baseband with 1 mounted radio

Why CRKIT Framework ? Focus on APP Development NOT complete Radio Abstract lower level design complexities from Users INNOVATION CYCLE Live system runs Focus on Creativity, not Engineering Complexity : Split Baseband into Static and Dynamic domains :  Static - Open-sourced System-on-Chip (complex engineering problem)  Dynamic – Swappable Communication APPs (creative problem) CRKIT = make real-time and wideband radio a viable solution for large scale experiments. Build Radio :  Non trivial effort  Substantial barrier to entry  Many engineering man-hours needed  Requires cross-disciplinary expertise CogRadio from RTS FPGA-based SoC Features  Access to lower level resources thru APIs  Networking capable node  Support up to four dynamic APPs  Library of Open-sourced Communication APPs  Can be ported to future HW platforms and newer FPGA technologies.

FSoC Overview FSoC currently consists of following major components : 1. Ethernet Port (static) Gigabit Ethernet rate frame synchronization frame generation/formatting 2. Packet Processor (static) Simple packet classification/forwarding scheme based on IP/UDP Control packets -> Processor Core Data packets -> APP 3. Application (dynamic) User specific designs e.g. simple QPSK/QAM, OFDM, FHSS, DSSS… Support up to 4 APPs simultaneously APPs can be swapped as needed by users 4. RF Port (static) interfacing to AD/DA 5. RMAP Processor (static) Sub-system interfacing and control Address decoding RF SPI Control 6. Processor Core (static) 32-bit Softcore processor interfacing to 32MB DRAM interfacing to 16MB FLASH Three distinct data flows through system: 1) APP/Processor Core to outbound ethernet port 2) Inbound ethernet port to APP 3) Inbound ethernet port to Processor Core

CRKIT Transport Layers Framework domain (static) Application domain (dynamic)  ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer.  IP Layer (Fast Path) –  Hardware based implementation  Only a subset of IP and UDP functions.  Fast track is reserved for APP data related traffic  Data IP packets are routed to the fast track based on specific UDP port number.  IP Layer (Slow Path) –  Software based implementation  Support TCP as this is done in SW e.g. processor core.  Slow track is reserved mostly for control related traffic : CRKit hardware configuration (register map access) and RF control.  Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track. Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field.  VRT Layer –  VITA Radio Transport layer, only a subset of VITA standard is supported.  VRT layer is optional, bypass this layer if not used.  VRT useful to mux multiple radio streams to a single pipe, and demux at the other end.  Standardized radio packet types: 1) Data for signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth. Framework Domain :  User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish.  Wireless PHY – again user specific implementation. Application Domain :

CRKIT Programming Model Network HOSTCRKIT Application development CRKIT development Comm. APP Embedded SW GUIAlgorithm System Debugging System Test HW Configuration IP Networking Mathworks Simulink CRDSA Host CMD Parsing VHDL/ Verilog DHCP/ARPETH/VITA Lookup Tables/ RF Java, C#CC

APP Development Flow MATLAB Simulink Flow CRKIT Flow APP Specification Design dynamic APP APP Validation Compile APP Link APP to Framework Compile Framework Generate FPGA bit file Download to Hardware PCORE boots Execute CRKIT Embedded SW Xilinx ISE Flow

CRKIT Example – QPSK Receiver

CRKIT Example – FPGA Utilization