Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 61 Lecture 6 Logic Simulation n What is simulation? n Design verification n Circuit modeling n True-value.

Slides:

Advertisements

Similar presentations

Verilog HDL -Introduction

Advertisements

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Logic Simulation.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei ECE 300 Advanced VLSI Design Fall 2006 Lecture 24: CAD Systems &

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 71 Lecture 7 Fault Simulation n Problem and motivation n Fault simulation algorithms n Serial n Parallel.

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4b1 Design for Testability Theory and Practice Lecture 4b: Fault Simulation n Problem and motivation.

Spring 08, Jan 31.. ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Timing Simulation and STA Vishwani D. Agrawal.

1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,

Lecture 5 Fault Simulation

11/2-4/04ELEC / ELEC / (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test.

Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.

9/29/05ELEC / Lecture 101 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

1 EECS Components and Design Techniques for Digital Systems Lec 21 – RTL Design Optimization 11/16/2004 David Culler Electrical Engineering and Computer.

Fall 2006, Oct. 17 ELEC / Lecture 9 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: Logic Level.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 81 Lecture 8 Testability Measures n Origins n Controllability and observability n SCOAP measures 

Spring 07, Mar 1, 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Simulation and STA Vishwani D. Agrawal.

مرتضي صاحب الزماني  The registers are master-slave flip-flops (a.k.a. edge-triggered) –At the beginning of each cycle, propagate values from primary inputs.

(1) Modeling Digital Systems © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.

8/28/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,

ECE 2372 Modern Digital System Design

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Logic Modeling.

Hardware Design Environment Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

ECE Advanced Digital Systems Design Lecture 12 – Timing Analysis Capt Michael Tanner Room 2F46A HQ U.S. Air Force Academy I n t e g r i.

1 H ardware D escription L anguages Modeling Digital Systems.

Module 1.2 Introduction to Verilog

Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.

Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics Modeling with hardware description languages (HDLs).

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).

IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.

Copyright 2001, Agrawal & BushnellLecture 6: Sequential ATPG1 VLSI Testing Lecture 6: Sequential ATPG n Problem of sequential circuit ATPG n Time-frame.

Introduction to ASIC flow and Verilog HDL

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

TOPIC : Types of Simulation UNIT 1 : Modeling Module 1.5 Simulation.

Copyright 2001, Agrawal & BushnellLecture 6:Fault Simulation1 VLSI Testing Lecture 6: Fault Simulation Dr. Vishwani D. Agrawal James J. Danaher Professor.

Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA

Chapter 3 Boolean Algebra and Digital Logic T103: Computer architecture, logic and information processing.

EECE 320 L8: Combinational Logic design Principles 1Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 8: Combinational Logic Design Principles.

COE 360 Principles of VLSI Design Delay. 2 Definitions.

Mohamed Younis CMCS 411, Computer Architecture 1 CMSC Computer Architecture Lecture 8 Hardware Design Languages February 21, 2001

Logic Simulation 1 Outline –Logic Simulation –Logic Design Description –Logic Models Goal –Understand logic simulation problem –Understand logic models.

ASIC Design Methodology

Combinational Logic Design

VLSI Testing Lecture 5: Logic Simulation

Discussion 2: More to discuss

Topics Modeling with hardware description languages (HDLs).

VLSI Testing Lecture 5: Logic Simulation

VLSI Testing Lecture 4: Testability Analysis

Vishwani D. Agrawal Department of ECE, Auburn University

VLSI Testing Lecture 6: Fault Simulation

Lecture 7 Fault Simulation

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES

Lecture 13 Sequential Circuit ATPG Time-Frame Expansion

VLSI Testing Lecture 6: Fault Simulation

Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-I]

Topics Modeling with hardware description languages (HDLs).

Lecture 10 Sequential Circuit ATPG Time-Frame Expansion

Hardware Description Languages

CS341 Digital Logic and Computer Organization F2003

Lesson 4 Synchronous Design Architectures: Data Path and High-level Synthesis (part two) Sept EE37E Adv. Digital Electronics.

VLSI Testing Lecture 8: Sequential ATPG

Modeling Languages and Abstract Models

VHDL Introduction.

VLSI Testing Lecture 9: Delay Test

VLSI Testing Lecture 7: Delay Test

VLSI Testing Lecture 3: Fault Modeling

Lecture 26 Logic BIST Architectures

Combinational Circuits

ELEC 7770 Advanced VLSI Design Spring 2012 Timing Simulation and STA

Presentation transcript:

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 61 Lecture 6 Logic Simulation n What is simulation? n Design verification n Circuit modeling n True-value simulation algorithms n Compiled-code simulation n Event-driven simulation n Summary

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 62 Simulation Defined n Definition: Simulation refers to modeling of a design, its function and performance. n A software simulator is a computer program; an emulator is a hardware simulator. n Simulation is used for design verification: n Validate assumptions n Verify logic n Verify performance (timing) n Types of simulation: n Logic or switch level n Timing n Circuit n Fault

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 63 Simulation for Verification True-value simulation Specification Design (netlist) Input stimuli Computed responses Response analysis Synthesis Design changes

A 32-bit ripple-carry adder Copyright 2001, Agrawal & BushnellVLSI Test: Lecture

Design verification Vectors for 4-bit adder circuit (functional correctness) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 6 5 Delay Test for longest path : C0 C4, vector 2,6(3,7) C4: 0 1

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture :Simulation for Test Evaluation Determines the Fault Coverage Produce a set of test vector

Test evaluation for single stuck at fault Four-bit adder Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 67

Reverse-Order simulation Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 68 Reverse-Order simulation cannot be used for sequential Circuits

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture : Modeling Circuits for Simulation n Modules, blocks or components described by n Input/output (I/O) function n Delays associated with I/O signals n Examples: binary adder, Boolean gates, FET, resistors and capacitors n Interconnects represent n ideal signal carriers, or n ideal electrical conductors n Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. ( HDL (Verilog ), VHDL)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 610 Modeling Levels and Type of simulaton Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z 0, 1 and X Analog voltage Analog voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Zero-delay Fine-grain timing Continuous time Modeling level Function, behavior, RTL Logic Switch Timing Circuit Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 611 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); a b c d e f HA FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry A2 O1 N1 O2

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 612 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b and C c are parasitic capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 613 Options for Inertial Delay (simulation of a NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=3 Transient region Unknown (X) X

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 614 Signal States n Two-states (0, 1) can be used for purely combinational logic with zero-delay. n Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. n Four-states (0, 1, X, Z) are essential for MOS devices. See example below. n Analog signals are used for exact timing of digital logic and for analog circuits. 0 0 Z (hold previous value)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 615

4 WeekFault-Tolerant System Design16 Level of Simulation  Register-level, for systems modeled entirely in RTL or as an interconnection of components modeled in RTL  Functional-level, for systems modeled as an interconnection of primitive functional blocks  Gate-level simulation;  Transistor-level (we consider logic level and not circuit-level analog simulation)  Mixed-level simulation

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 617 True-Value Simulation Algorithms n Compiled-code simulation n Applicable to zero-delay combinational logic n Also used for cycle-accurate synchronous sequential circuits for logic verification n Efficient for highly active circuits, but inefficient for low-activity circuits n High-level (e.g., C language) models can be used n Event-driven simulation n Only gates or modules with input events are evaluated (event means a signal change) n Delays can be accurately simulated for timing verification n Efficient for low-activity circuits n Can be extended for fault simulation

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 618 Compiled-Code Algorithm n Step 1: Levelize combinational logic and encode in a compilable programming language n Step 2: Initialize internal state variables (flip- flops) n Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) n Execute compiled code Report or save computed variables

4 WeekFault-Tolerant System Design19 Compiled Simulation  Delay can be modeled by Explicitly adding them to Software model

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 620

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 621

4 WeekFault-Tolerant System Design22 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); OR: O1, (a, b), (d); NOT: N1, (c), (e); AND: A2, (d, e), (f); a b c d e f FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry A1A1 O1O1 A2A2 N1N1 o2o2

4 WeekFault-Tolerant System Design23 Asynchronous circuit simulation with compiled-code model

4 WeekFault-Tolerant System Design Correct model for compiled simulation Shows that a compiled simulator cannot deal with Races and hazards

4 WeekFault-Tolerant System Design25 Main flow of event-driven simulation

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 626 Event-Driven Algorithm (Example) a =1 b =1 c =1 0 d = 0 e =1 f =0 g =1 Time, t g t = Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 627 Time Wheel (Circular Stack) t= max Current time pointer Event link-list

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 628 Efficiency of Event- driven Simulator n Simulates events (value changes) only n Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Large logic block without activity Steady 0 0 to 1 event Steady 0 (no event)

4 WeekFault-Tolerant System Design29 Delay Models  Delay modeling is a key element controlling the trade-off between the accuracy and the complexity of the simulation algorithm.  Delay Modeling for gates:

4 WeekFault-Tolerant System Design30

4 WeekFault-Tolerant System Design31 d dfdf drdr Transition- independent delay model d I =4 d I =2 d

4 WeekFault-Tolerant System Design32 Output Inertial Delay

4 WeekFault-Tolerant System Design33 Delay Modeling for Functional element

4 WeekFault-Tolerant System Design34 Wire delays Modeled by delay element

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 635 Summary n Logic or true-value simulators are essential tools for design verification. n Verification vectors and expected responses are generated (often manually) from specifications. n A logic simulator can be implemented using either compiled-code or event-driven method. n Per vector complexity of a logic simulator is approximately linear in circuit size. n Modeling level determines the evaluation procedures used in the simulator.