© Digital Integrated Circuits 2nd Design Methodologies Sequential Logic 2 storage mechanisms positive feedback charge-based

© Digital Integrated Circuits 2nd Design Methodologies A simple example of sequential design A one-input, one-output system receives a binary sequence (one bit at each clock cycle) and produces another binary sequence such that the output is 1 whenever a leading subsequence of odd 0s and odd 1s is recognized in the input sequence. For example, the input sequence of …… causes the output

© Digital Integrated Circuits 2nd Design Methodologies Digital Integrated Circuits A Design Perspective VLSI Design Methodologies Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el

© Digital Integrated Circuits 2nd Design Methodologies Design Abstraction Levels n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM

© Digital Integrated Circuits 2nd Design Methodologies The Design Productivity Challenge Source: sematech97  A growing gap between design complexity and design productivity  Designing a multi-million transistor circuit is not possible without good design methodologies and computer tools

© Digital Integrated Circuits 2nd Design Methodologies A Simple Processor MEMORY DATAPATH CONTROL INPUT/OUTPUT  These components occurs in almost all processors  Datapath is core of the processor. A typical datapath consists of logic units (AND, OR, XOR etc) and arithmetic operators (ADDER, MULTIPLIER, COMPARATOR, SHIFTER etc)  Control unit can be viewed as a finite state machine.  Memory stores data and instructions.

© Digital Integrated Circuits 2nd Design Methodologies A Simple Processor  What might be abstracted away from the schematic is interconnection networks, such as on-chip buses, clock and power distribution networks.  For a long time, interconnection network was a afterthought, but due to technology migration, interconnects presents capacitive, resistive and inductive effects, which might affect the system performance. MEMORY DATAPATH CONTROL INPUT/OUTPUT

© Digital Integrated Circuits 2nd Design Methodologies A System-on-a-Chip: Example Courtesy: Philips The simple structure shown in previous slide can be repeated many times on silicon, e.g. a IC chip for HDTV

© Digital Integrated Circuits 2nd Design Methodologies Impact of Implementation Choices  Choosing an effective implementation approach strongly depends on the function of the modules under consideration.  The choice of implementation can have a tremendous effect on the quality of the final product.  A design with flexibility is very attractive from application point of view. But it comes at a price in both performance and power efficiency.  Providing flexibility also means additional hardware overhead.  Hardware/software co-design (partitioning, task scheduling, resource allocation etc)

© Digital Integrated Circuits 2nd Design Methodologies Impact of Implementation Choices Energy Efficiency (in MOPS/mW) Flexibility (or application scope) None Fully flexible Somewhat flexible Hardwired custom Configurable/Parameterizable Domain-specific processor (e.g. DSP) Embedded microprocessor

© Digital Integrated Circuits 2nd Design Methodologies Design Methodology Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps

© Digital Integrated Circuits 2nd Design Methodologies Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital VLSI Implementation Approaches A number of distinct implementation approaches ranging from high-performance, handcrafted design to fully programmable medium-to-low performance design

© Digital Integrated Circuits 2nd Design Methodologies The Custom Approach  When performance or design density is of primary importance, handcrafting the design (at both logic level and layout level) seems to be the only option.  The labor–intensive nature of custom design translates into a high cost and long time to market. So, it should be used only under some conditions.  With continuous progress in design automation tools and rapid increase of circuit complexity, full- custom design is reducing.  In fact, library cell design is the only area where custom design still thrives today.  Design support/assistance tools are needed.

© Digital Integrated Circuits 2nd Design Methodologies The Custom Approach Intel 4004 Courtesy Intel

© Digital Integrated Circuits 2nd Design Methodologies Transition to Automation and Regular Structures Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8286 Intel 8486 Courtesy Intel

© Digital Integrated Circuits 2nd Design Methodologies Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital VLSI Implementation Approaches A number of distinct implementation approaches ranging from high-performance, handcrafted design to fully programmable medium-to-low performance design

© Digital Integrated Circuits 2nd Design Methodologies Cell-based Design  Since custom-design approach proves to be prohibitively expensive, a wide variety of design approaches have been introduced to shorten and automate the design process.  The idea behind cell-based design is to reduce the implementation effort by reusing a library of limited cells.  The advantage of the approach is that the cells only need to be designed and verified once for a given technology, and can be reused many times.  The disadvantage is that constrained nature of the library reduces the possibility of fine-tuning the design.  Cell-based approaches can be partitioned into a number of classes depending on the granularity of the library elements.

© Digital Integrated Circuits 2nd Design Methodologies Cell-based Design (or standard cells)  Cells are placed in rows that are separated by routing channels. This requires that all cells have equal height.  Routing channel requirements are reduced by feedthrough cells and more interconnect layers (three dimensional designs) Standard cell approach standardizes the design entry level at the logic gate.

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell — Example [Brodersen92] Today’s standard cell typically employs many versions of each cell, sized for different driving strengths, as well as performance and power consumption level. It is left to synthesis tools to select the correct cells.

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell – The New Generation Cell-structure hidden under interconnect Layers (more interconnect layers). Only a small fraction of the area is wasted for interconnect.

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell - Example 3-input NAND cell (from ST Microelectronics 0.18um): C = Load capacitance T = input rise/fall time

© Digital Integrated Circuits 2nd Design Methodologies A Historical Perspective: the PLA x 0 x 1 x 2 AND plane x 0 x 1 x 2 Product terms OR plane f 0 f 1

© Digital Integrated Circuits 2nd Design Methodologies Two-Level Logic Inverting format (NOR- NOR) more effective Every logic function can be expressed in sum-of-products format (AND-OR) minterm

© Digital Integrated Circuits 2nd Design Methodologies PLA Layout – Exploiting Regularity V DD GND  And-Plane Or-Plane

© Digital Integrated Circuits 2nd Design Methodologies Breathing Some New Life in PLAs River PLAs  A cascade of multiple-output PLAs.  Adjacent PLAs are connected via river routing. No placement and routing needed. Output buffers and the input buffers of the next stage are shared. Courtesy B. Brayton

© Digital Integrated Circuits 2nd Design Methodologies Compiled Cell / Automatic Cell Generation Courtesy Acadabra Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell Customized cells are still attractive, hence automated cell generation with adjusted sizes is needed

© Digital Integrated Circuits 2nd Design Methodologies Macro/Mega Modules and IP blocks  Standardizing at the logic-gate level is attractive for random logic functions, but it turns out to be inefficient for more complex structures such as data paths, memory, microprocessor etc.  By capturing the specific nature of some larger blocks, implementations can be obtained that outperform the standard cell approach.  Cells with a complexity that surpasses what is found in a typical standard cell library are called macrocells/megacells.  Macrocells can also be identified as hard macro or soft macro.

© Digital Integrated Circuits 2nd Design Methodologies Hard macrocell  A hard macro cell represents a module with a given functionality and a pre-determined physical design.  In essence, a hard macro represents a custom design of the requested function (in some cases with parameterization)  The advantage of the hard macro is that it brings with it all the good properties of custom design, and can be reused many times.  The disadvantage is that it is hard to port the design to other technologies.

© Digital Integrated Circuits 2nd Design Methodologies A hard parameterized macrocell 256  32 (or 8192 bit) SRAM in 0.18um technology Generated by hard-macro module generator/compiler

© Digital Integrated Circuits 2nd Design Methodologies Soft MacroModules Synopsys Design Compiler Soft macro represents a module with a given functionality without a specific implementation, which may vary from instance to instance. It relies more on the semi-custom design approaches. (Mostly need standard cell at lower level).

© Digital Integrated Circuits 2nd Design Methodologies “Intellectual Property”  Nowdays, with increasing complexity, circuits are built with more and more reusable building blocks of increasing complexity.  Typically, these modules are acquired from third-party vendors. Macrocells distributed in this way are called Intellectual Property (IP).  Good examples of IP are embedded microprocessors and microcontrollers, DSP processors, FFT module, filter modules, error-correction modules, encoding and decoding modules, etc.  Design of a complex system is becoming an exercise of reuse in different levels of granularity. Future system will use a blend of design styles and design modules.

© Digital Integrated Circuits 2nd Design Methodologies A Protocol Processor for Wireless IP block Soft macrocells Custom module

© Digital Integrated Circuits 2nd Design Methodologies Semicustom (cell-based) Design Flow HDL Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Capture Design Iteration Cadence Encounter (Synopsys design compiler) Cadence Encounter Cadence Primetime (Thermal, timing, noise analysis)

© Digital Integrated Circuits 2nd Design Methodologies The “Design Closure” Problem Courtesy Synopsys Iterative Removal of Timing Violations (white lines) At deep sub-micron, layout parasitics plays an important role. A design is forced to go though a number of iterations to have all timing constraints met. This is called “timing closure”.

© Digital Integrated Circuits 2nd Design Methodologies Integrating Synthesis with Physical Design Physical Synthesis RTL(Timing) Constraints Place-and-Route Optimization Artwork Netlist with Place-and-Route Info Macromodules Fixed netlists

© Digital Integrated Circuits 2nd Design Methodologies Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches A number of distinct implementation approaches ranging from high-performance, handcrafted design to fully programmable medium-to-low performance design

© Digital Integrated Circuits 2nd Design Methodologies Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Late-Binding Implementation  All design methodologies discussed thus far require a complete run through design and fabrication process, which might lengthen time-to-market.  Consequently, a number of alternative implementation approaches are proposed that do not require a complete run through the manufacturing process, or they avoid dedicated processing completely.

© Digital Integrated Circuits 2nd Design Methodologies Pre-diffused Gate Arrays / Sea-of-gates  In this approach, batches of wafers containing arrays of primitive cells or transistors are manufactured by the vendors.  All fabrication steps needed to make the transistors are standardized and executed without regard to the final application.  To transform these uncomitted wafers to an actual design, only the desired interconnections have to be added.

© Digital Integrated Circuits 2nd Design Methodologies Pre-diffused Gate Arrays: Sea-of-gates Uncommited Cell Committed Cell (4-input NOR) Contact predefined The primary challenge is to determine the composition of primitive cell and the size of transistors such that the gate array template can be utilized to a maximal extent over a wide range of designs.

© Digital Integrated Circuits 2nd Design Methodologies Sea-of-gate Primitive Cells Using oxide-isolationUsing gate-isolation

© Digital Integrated Circuits 2nd Design Methodologies Example: Base Cell of Gate-Isolated GA From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Example: register in Gate-Isolated GA From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6  m CMOS) Courtesy LSI Logic Utilization factor varies depending on the application.

© Digital Integrated Circuits 2nd Design Methodologies The return of gate arrays? metal-5 metal-6 Via-programmable cross-point programmable via Via programmable gate array (VPGA) [Pileggi02] Exploits regularity of interconnect

© Digital Integrated Circuits 2nd Design Methodologies Pre-wired Arrays  Pre-diffused arrays offer a faster road to implementation, but it would be even better if dedicated manufacturing steps could be avoided.  This leads to pre-processed die that can be programmed in the file to implement any logic function, called Field Programmable Logic Array (FPGA).  Two main issues in FPGA: how to store the programmability and how to implement the programmability

© Digital Integrated Circuits 2nd Design Methodologies Pre-wired Arrays  Programming Technique (how to store?)  Fuse-based (program-once)  Non-volatile EEPROM based (read-only memory)  RAM based

© Digital Integrated Circuits 2nd Design Methodologies Fuse-Based FPGA antifuse polysilicon n + antifuse diffusion 2 l From Smith97 Open by default, closed by applying current pulse, only one-time programmable

© Digital Integrated Circuits 2nd Design Methodologies Nonvolatile EEPROM FPGA From Smith97  Memory stores its value even when power is down (flash memory or EEPROM)  Once programmed, the logic remains functional until a new programming round.  Extra complexity and cost

© Digital Integrated Circuits 2nd Design Methodologies Non-volatile memory  the transistor has two gates, a control gate (CG) and a floating gate (FG) insulated all around by an oxide layer.  The FG is interposed between the CG and the MOS channel.  Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years.  When the FG holds a charge, it partially cancels the electric field from the CG, which modifies the V T of the cell.  During read-out, a voltage is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the VT of the cell, which is in turn controlled by charge on the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data.

© Digital Integrated Circuits 2nd Design Methodologies Non-volatile memory

© Digital Integrated Circuits 2nd Design Methodologies Volatile RAM FPGA From Smith97  By far the most popular approach  Static RAM used, so lose value when power down. Thus, a re-loading of the program from an external permanent memory is needed every time power is on  Parallel interface is needed for today’s large size program

© Digital Integrated Circuits 2nd Design Methodologies Pre-wired Arrays  Programmable Logic (how to implement programmability?) For logic function  Array-Based  Look-up Table For interconnect  Channel-routing  Mesh networks

© Digital Integrated Circuits 2nd Design Methodologies Array-Based Programmable Logic PLAPROMPAL O 1 O 2 O 3 Programmable AND array Programmable OR array O 1 O 2 O 3 Programmable AND array Fixed OR array Indicates programmable connection Indicates fixed connection The later two are variants of the first one with one plane fixed

© Digital Integrated Circuits 2nd Design Methodologies Programming a PROM f 0 1X 2 X 1 X 0 f 1 NA : programmed node x2x1x0x2x1x0

© Digital Integrated Circuits 2nd Design Methodologies More Complex PAL From Smith97 i inputs, j minterms/macrocell, k macrocells

© Digital Integrated Circuits 2nd Design Methodologies 2-input MUX as programmable logic block F A0 B S 1 Configuration ABSF= X1X 0Y1Y 0YXXY X0Y Y0X Y1XX + Y 10X 10Y 1111 X Y =AS+BS

© Digital Integrated Circuits 2nd Design Methodologies Logic Cell of Actel Fuse-Based FPGA

© Digital Integrated Circuits 2nd Design Methodologies Look-up Table Based Logic Cell Programmable memory

© Digital Integrated Circuits 2nd Design Methodologies LUT-Based Logic Cell Courtesy Xilinx D 4 C 1....C 4 x xxxxx D 3 D 2 D 1 F 4 F 3 F 2 F 1 Logic function of xxx Logic function of xxx Logic function of xxx xx 4 x xx xxxx H P Bits control Bits control Multiplexer Controlled by Configuration Program x x x x xx x xxxx x xx xxxx xx x x Xilinx 4000 Series

© Digital Integrated Circuits 2nd Design Methodologies Array-Based Programmable Wiring Input/output pinProgrammed interconnection Interconnect Point Horizontal tracks Vertical tracks Cell

© Digital Integrated Circuits 2nd Design Methodologies Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies Transistor Implementation of Mesh Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies Altera MAX From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Altera MAX Interconnect Architecture row channelcolumn channel LAB Courtesy Altera Array-based (MAX ) Mesh-based (MAX 9000)

© Digital Integrated Circuits 2nd Design Methodologies Xilinx 4000 Interconnect Architecture CLB 8484 Quad Single Double Long Direct Connect Direct Connect QuadLongGlobal Clock LongDoubleSingleGlobal Clock Carry Chain Long 1244 Courtesy Xilinx

© Digital Integrated Circuits 2nd Design Methodologies RAM-based FPGA Xilinx XC4000ex Courtesy Xilinx

© Digital Integrated Circuits 2nd Design Methodologies About FPGA Xilinx XC4000ex Courtesy Xilinx  To make array-based approach successful, advanced software support in terms of cell placement, signal routing and synthesis is required.  Programmable logic is at least 10 times less efficient in terms of energy and performance with respect to ASIC (Application Specific Integrated Circuit) and custom designs.

© Digital Integrated Circuits 2nd Design Methodologies Design at a crossroad System-on-a-Chip RAM 500 k Gates FPGA + 1 Gbit DRAM Preprocessing Multi- Spectral Imager  C system +2 Gbit DRAM Recog- nition Analog 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS  Embedded applications where cost, performance, and energy are the real issues!  DSP and control intensive  Mixed-mode  Combines programmable and application-specific modules  Tools plays crucial role Hybrid implementation seems to be the future!

© Digital Integrated Circuits 2nd Design Methodologies Heterogeneous Programmable Platforms Xilinx Vertex-II Pro Courtesy Xilinx High-speed I/O Embedded PowerPc Embedded memories Hardwired multipliers FPGA Fabric

© Digital Integrated Circuits 2nd Design Methodologies Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations Source: Theo Claasen (Philips) – DAC 00

© Digital Integrated Circuits 2nd Design Methodologies Architecture ReUse  Silicon System Platform  Flexible architecture for hardware and software  Specific (programmable) components  Network architecture  Software modules  Rules and guidelines for design of HW and SW  Has been successful in PC’s  Dominance of a few players who specify and control architecture  Application-domain specific (difference in constraints)  Speed (compute power)  Dissipation  Costs  Real / non-real time data

© Digital Integrated Circuits 2nd Design Methodologies Platform-Based Design  A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer  New platforms will be defined at the architecture-micro-architecture boundary  They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations  Key to such approaches is the representation of communication (interconnect) in the platform model “Only the consumer gets freedom of choice; designers need freedom from choice” (Orfali, et al, 1996, p.522) Source: R. Newton

© Digital Integrated Circuits 2nd Design Methodologies Summary  Digital CMOS Design is kicking and healthy  Who can afford design in the years to come? Some major design methodology change in the making!