1 CSE370, Lecture 24 Lecture 26 u Logistics n HW8 due Friday n Ant extra credit due Friday n Final exam a week from today, 12/8 8:30am-10:20am here n Review time/place TBA u Last lecture n Simplification u Today n State encoding íOne-hot encoding íOutput encoding 26

2 CSE370, Lecture 24 Example: A vending machine u 15 cents for a cup of coffee u Doesn’t take pennies or quarters u Doesn’t provide any change n FSM-design procedure 1.State diagram 2.state-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6. Implement the design 26 Vending Machine FSM N D Reset Clock Open Coin Sensor Release Mechanism

3 CSE370, Lecture 24 A vending machine: State minimization 26 symbolic state table presentinputsnextoutput stateDNstateopen 0¢00 0¢0 01 5¢0 1010¢0 11–– 5¢00 5¢0 0110¢0 1015¢0 11–– 10¢0010¢0 0115¢0 1015¢0 11–– 15¢––15¢1 0¢ Reset 5¢ N N N + D 10¢ D 15¢ [open] D

4 CSE370, Lecture 24 A vending machine: State encoding 26 present stateinputsnext stateoutput Q1Q0DND1D0open ––– ––– ––– 11–– 111

5 CSE370, Lecture 24 A vending machine: Logic minimization 26 D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q X X 1 1 Q1 D1 Q0 N D X X Q1 D0 Q0 N D X X 1 X Q1 Open Q0 N D

6 CSE370, Lecture 24 A vending machine: Implementation 26

7 CSE370, Lecture 24 State encoding u Assume n state bits and m states n 2 n ! / (2 n – m)! possible encodings íExample: 3 state bits, 4 states, 1680 possible state assignments u Want to pick state encoding strategy that results in optimizing your criteria n FSM size (amount of logic and number of FFs) n FSM speed (depth of logic and fan-in/fan-out) n FSM ease of design or debugging 26

8 CSE370, Lecture 24 State-encoding strategies u No guarantee of optimality n An intractable problem u Most common strategies n Binary (sequential) – number states as in the state table n Random – computer tries random encodings n Heuristic – rules of thumb that seem to work well íe.g. Gray-code – try to give adjacent states (states with an arc between them) codes that differ in only one bit position n One-hot – use as many state bits as there are states n Output – use outputs to help encode states n Hybrid – mix of a few different ones (e.g. One-hot + heuristic) 26

9 CSE370, Lecture 24 One-hot encoding u One-hot: Encode n states using n flip-flops n Assign a single “1” for each state íExample: 0001, 0010, 0100, 1000 n Propagate a single “1” from one flip-flop to the next íAll other flip-flop outputs are “0” u The inverse: One-cold encoding n Assign a single “0” for each state íExample: 1110, 1101, 1011, 0111 n Propagate a single “0” from one flip-flop to the next íAll other flip-flop outputs are “1” u “almost one-hot” encoding (modified one-hot encoding) n Use no-hot (000…0) for the initial (reset state) n Assumes you never revisit the reset state till reset again. 26

10 CSE370, Lecture 24 One-hot encoding (con’t) u Often the best/convenient approach for FPGAs n FPGAs have many flip-flops u Draw FSM directly from the state diagram n + One product term per incoming arc n - Complex state diagram  complex design n - Many states  many flip flops 26

11 CSE370, Lecture 24 Example: A vending machine … again u 15 cents for a cup of coffee u Doesn’t take pennies or quarters u Doesn’t provide any change n FSM-design procedure 1.State diagram 2.state-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6. Implement the design 26 Vending Machine FSM N D Reset Clock Open Coin Sensor Release Mechanism

12 CSE370, Lecture 24 One-hot encoded transition table – – –– – – – –– – – – –– – 1000 – – present state inputs next state output Q 3 Q 2 Q 1 Q 0 D N D 3 D 2 D 1 D 0 open 0¢0¢ Reset 5¢5¢ N N N + D 10¢ D 15¢ [open] D D' N' 1 26

13 CSE370, Lecture 24 Designing from the state diagram 0¢0¢ Reset 5¢5¢ N N N + D 10¢ D 15¢ [open] D D' N' 1 D 0 = Q 0 D’N’ D 1 = Q 0 N + Q 1 D’N’ D 2 = Q 0 D + Q 1 N + Q 2 D’N’ D 3 = Q 1 D + Q 2 D + Q 2 N + Q 3 OPEN = Q 3 26

14 CSE370, Lecture 24 Output encoding u Reuse outputs as state bits n Why create new functions when you can use outputs? n Bits from state assignments are the outputs for that state íTake outputs directly from the flip-flops u ad hoc - no tools n Yields small circuits for most FSMs Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs 26

15 CSE370, Lecture 24 Vending machine --- already in output encoding form 0¢0¢ Reset 5¢5¢ N N N + D 10¢ D 15¢ [open] D D' N' 1 D 0 = Q 0 D’N’ D 1 = Q 0 N + Q 1 D’N’ D 2 = Q 0 D + Q 1 N + Q 2 D’N’ D 3 = Q 1 D + Q 2 D + Q 2 N + Q 3 OPEN = Q 3 26

16 CSE370, Lecture 24 Example: Digital combination lock u An output-encoded FSM n Punch in 3 values in sequence and the door opens n If there is an error the lock must be reset n After the door opens the lock must be reset n Inputs: sequence of number values, reset n Outputs: door open/close resetvalue open/closed new clock 26

17 CSE370, Lecture 24 Separate data path and control u Design datapath first n After the state diagram n Before the state encoding u Control has 2 outputs n Mux control to datapath n Lock open/closed reset open/closed new C1C2C3 comparator value equal multiplexer controller mux control clock

18 CSE370, Lecture 24 Draw the state diagram closed mux=C1 start equal & new not equal & new not new S0S1S2S3 ERR closed mux=C2 equal & new closed mux=C3 equal & new open 26

19 CSE370, Lecture 24 C1C2C3 comparator equal multiplexer mux control value C1 i C2 i C3 i mux control value i equal Design the datapath u Choose simple control n 3-wire mux for datapath íControl is 001, 010, 100 n Open/closed bit for lock state íControl is 0/1 26

20 CSE370, Lecture 24 Output encode the FSM u FSM outputs n Mux control is 100, 010, 001 n Lock control is 0/1 u State are: S0, S1, S2, S3, or ERR n Can use 3, 4, or 5 bits to encode n Have 4 outputs, so choose 4 bits íEncode mux control and lock control in state bits íLock control is first bit, mux control is last 3 bits S0 = 0001 (lock closed, mux first code) S1 = 0010 (lock closed, mux second code) S2 = 0100 (lock closed, mux third code) S3 = 1000 (lock open) ERR = 0000 (error, lock closed) 26

21 CSE370, Lecture 24 FSM has 4 state bits and 2 inputs... u Output encoded! n Outputs and state bits are the same u How do we minimize the logic? n FSM has 4 state bits and 2 inputs (equal, new) n 6-variable kmap for all five states? u Notice the state assignment is close to one-hot n ERR state (0000) is only deviation n Is there a clever design we can use? 26

22 CSE370, Lecture 24 Encode 4 state bits closed mux=C1 start equal & new not equal & new not new S0S1S2S3 ERR closed mux=C2 equal & new closed mux=C3 equal & new open S 0 + = S 0 N’ S 1 + = S 0 EN + S 1 N’ S 2 + = S 1 EN + S 2 N’ S 3 + = S 2 EN + S 3 A clever way for ERR is to use Preset/reset in existing flipflops. 26 Preset 0 = start Preset 1,2,3 = 0 Reset 0 = start’(E’N + (Q 0 +Q 1 +Q 2 +Q 3 )’) Reset 1,2,3 = start + (E’N + (Q 0 +Q 1 +Q 2 +Q 3 )’) Not equal & new Already in ERR

23 CSE370, Lecture 24 D 0 = Q 0 N’ D 1 = Q 0 EN + Q 1 N’ D 2 = Q 1 EN + Q 2 N’ D 3 = Q 2 EN + Q 3 Preset 0 = start Preset 1,2,3 = 0 Reset 0 = start’(E’N + (Q 0 +Q 1 +Q 2 +Q 3 )’) Reset 1,2,3 = start + (E’N + (Q 0 +Q 1 +Q 2 +Q 3 )’) 26 S0 S2 S1 S3 S0 S0 E N S1 N’ S1 E N S2 N’ S2 E N S0 S1 S2 S3

24 CSE370, Lecture 24 FSM design n FSM-design procedure 1.State diagram 2.state-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6. Implement the design 26