Sub-picosecond event timing system N-PET Ivan Prochazka*, Petr Panek presented at Shanghai Observatory, Academy of Sciences of China Nandan Road 80, Shanghai, China August 2009 * Czech Technical University in Prague Institute of Photonics and Electronics, Academy of Sciences of the Czech Republic, Prague, Czech Republic

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Outline n Novel timing principle of sub-ps event timing New technologies in electronics applied n Device development, design and construction n Timing properties: jitter, linearity, stability n Device operation n Operating modes & Firmware versions n Operational software package

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 n Time measurement is carried out in a FREQUENCY DOMAIN n The time-interpolation by the SAW filter n The SAW filter output synchronously sampled & digitized n Time / epoch is computed using the reverse FFT New timing principle theory by Petr Panek US Patent, 2005

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Device design n Based on theoretical papers and patents by P.Panek, significant part of NPET costs are patent payments (!) n Selected optimal combination of SAW filter central frequency, bandwidth,... n Based entirely on commercial components n The clock reference – 200 MHz Frequency Module designed and constructed by J.Kolbl and P.Sperber, Univ. of Deggendorf n On the input stage employed the fastest available components, n The device designed as modular, two channel event timer to enable independent modules modification and upgrade

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 New technologies employed n Ultrafast SiGe 10 GHz logic 35 ps slopes 50 Ohms lines matched drift ~ 0.5 ps / K n logical gain 1 high costs, limited availability PCB design, soldering problems n SAW filtersused as time interpolators n 200 MHz Module, J.Kolbl and P.Sperber,Deggendorf, 2005 extreme spectral purity n Circuit design complementary signals = > “NO GROUND” maximum design symetry ~ 10 ps delay matched cables

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Technology challenges n PCB design “Sampler” Advaced PCB design SW crashed due to board complexity n Equal signal path delay requirement (PCB + cable + PCB) < 10 ps (!!) n On board micro-strip ps delay lines n Sub - mm cable length tolerances (!!) n Soldering of some SMD chips factory only n FPGA and device control programming

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 First sample – single channel seft-test Power supply SAW filter Exciter Sampler & A/D data interface

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Device construction Event timer in operational configuration – NO Input board Exciter SAW filter Sampler and AD converter USB 2

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Device operational test – 2 channels

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 N-PET internal signals #1 Exciter output

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 N-PET internal signals SAW filter – interpolator output

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 N-PET internal signals SAW filter – interpolator output Power Spectral Density on SAW filter output Broad peak TV channel, narrow peaks ? Frequency in 0.1 MHz above 500 MHz

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Timing jitter - cable delay test Jitter per channel ~ 920 fs, normal distribution Review of Scientific Instruments, 78,1 (2007)

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Timing linearity - the worst case phase 21 st harmonics Amplitude 0.8 ps

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Timing linearity – optimized Amplitude < 200 fs Optimized RF signal amplitude on SAW filter input Review of Scientific Instruments, 80, (2009)

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 SLR tests in Graz, 4.3 km ground target New PET Graz ET Dassault 8.0 ps jitter 7.1 ps jitter Normal distribution (!!) The difference corresponds to 2.5 ps versus 0.9 ps for Dassault and NPET timing jitters 100 Hz laser operation, 25 Hz NPET reading

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 N-PET Input board n Adjustable level, slope pulse length 3 ns … 3 us n Gated inputs n Indicating LEDs n Linear power stabilizers n Temperature sensor n Ultrafast SiGe logic & symetrical desigh n Complementary outputs, 150 ps slopes n = > negligible jitter increase negligible drifts

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 N-PET Revision 2.0 for SAO n Original boards (!) n New power supplies n New cabling / piplining n New RF shielding n New heat management n New housing and mechanical design

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 n Operation Mode 1, 25 Hz, including Input board n NO airconditioning, No air blow n Rb frequency standard 10 Mhz n NIM input pulses, fall times ~ 150 ps n Trigger levels /default/ V, fall, no gate n 3 sigma filtering N-PET Revision 2.0 tests setup

I.Prochazka, P.Panek, SHAO, Shanghai, China, August MHz Frequency source J.Kolbl and P.Sperber, University of Applied Sciences, Deggendorf Risetime < 40 ps Clock jitter << 1 psec

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Timing jitter (Tb-Ta) N-PET Rev. 2.0 n Direct Input n 1.32 ps = > 0.92 ps / channel n Via Input board n 1.51ps = > 1.05 ps / channel

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Slopes < 100 ps / 100 mV over trigger level Needed fot tope performance Timing jitter versus pulse fall times N-PET Rev. 2.0

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Temperature drift (Tb-Ta) after Power ON N-PET Rev. 2.0 Interval change < 1.5 ps Drift < 0.1 ps / K 5 hours / screen Warm UP time ~ 2 hours Internal temp. t air +17 o C

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Temperature drift (Tb-Ta) after Power ON N-PET Rev. 2.0

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Timing linearity (Tb-Ta) N-PET Rev. 2.0 The best fit of the data, (solid curve). Note peak to peak non-linearity < +/- 200 fs over an entire range

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 NO saturation Tdev test N-PET Rev. 2.0

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Firmware and Operating modes n Firmware for the FPGA Xilinx u internal pulse distribution control u self calibration control u data collection from AD converters u data buffering u data flow control via USB 1 n FW covered by patented procedures, locked n MODE 1 – “hand shake mode” “on demand” on shot by shot basis robust and easy to operate rate 25 Hz max, limited by USB 1 latency fw installed as default n MODE 2 – cycle of measurements (endless loop) rate ~ 300 Hz, limited by driver used, may be improved ! available in Prague with download instructions October 2009

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Data processing in PC n Purpose – converting the sampled and digitized wavefronts data into epochs n Recursive (“selflearning”) algorithm dedicated for repeated measurements n The device self-calibration is included n Complicated algorithm consisting of a numer of compex double precision arrays manipulation, multiple FFT etc. n See attached list for ~ 10% of the description (patent pending) n High CPU and data volume requirements Time consuming, repetition rate limit 

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Data acquisition and processing sw - MODE 1 n C++ language n Main program + sub. source n Standard C++ libraries n Dedicated libraries“ n Program TIMU loop over measurements two independent channels 25 bit counter reading 10 ns vernier reading 0.1 ps PS Bios time stamps progress bar

I.Prochazka, P.Panek, SHAO, Shanghai, China, August 2009 Conclusion n Sub – picosecond event timing device is existing n “