Computer Arithmetic

Integer Representation Sign-magnitude representation ’s complement representation magnitudes

Addition / Subtraction Hardware M=0 addition A ← A + B M=1 subtraction A ← A + B +1 A register Enable Carry-in complementer Adder B register M C Carry-out V

Addition / Subtraction Algorithm 2’s complement Overflow V=1 if XOR of the last two carries is 1 V=0 otherwise AdditionSubtraction A ← A + B V←overflow A ← A + B + 1 V←overflow A register Enable Carry-in complementer Adder B register M C Carry-out V

Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+ B +1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0=1 A s =B s A s ≠B s

Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+B+1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0=1 A s =B s A s ≠B s Ex: (+3)+(+5) A s =0 A=0011 B s =0 B=0101 A s  B s =0A+B=1000 C=0 V=0 Result: A s =0A=1000 Ex: (-3) − (+5) A s =1 A=0011 B s =0 B=0101 A s  B s =1A+B=1000 C=0 V=0 Result: A s =1A=1000

Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+B+1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0 =1 A s =B s A s ≠B s Ex: (+5) + (-3) A s =0 A=0101 B s =1 B=0011B+1=1101 A s  B s =1A+B+1=0010 C=1 V=0 Result: A s =0A=0010 Ex: (-3) − (-5) A s =1 A=0011 B s =1 B=0101B+1=1011 A s  B s =1A+B+1=1110 C=0 V= =0010 Result: A s =0A=0010

Multiplication Hardware A register Adder Q registerC B register Q0Q0 Q -1

Multiplication Algorithm Sign-magnitude Ex: 3 * 5 M s =0 M=0011 (multiplicand) Q s =0 Q=0101(multiplier) Result: A s =0 (M s  Q s ) AQ= CAQ A ← A+M00011 Shift right Shift right A ← A+M00011 Shift right Shift right

Multiplication Algorithm 2’s complement (Booth’s Alg.) Ex: (-3) * 5 M=1101 (multiplicand) M+1=0011 Q=0101 (multiplier) Result: AQ= = -15 AQQ A ← A - M0011 Arith. Shift right A ← A + M1110 Arith. Shift right A ← A - M0010 Arith. Shift right A ← A + M1110 Arith. Shift right

Division Hardware A register Adder Q registerC B register Q0Q0

Division Algorithm Sign-magnitude Ex: 14  5 M s =0 M=5=0101 (divisor) M+1=1011 Q s =0 Q=14=1110 (dividend) Result: A s =0 (M s  Q s ) Q=0010 (quotient) A=0100 (remainder) AQ Shift left A ← A - M1100 A<0 A ← A + M0001 Shift left A ← A - M A<0 A ← A + M0011 Shift left A ← A - M A>0 Shift left A ← A - M A<0 A ← A + M0100

Floating-point Representation mantissa x radix exponent radix=2 Sign-magnitude 2’s complement representation mantissaexponents (significand)

Biased Representation integerno bias2 k-1 (=8)2 k-1 -1 (=7) mantissa x radix exponent radix=2 Sign-magnitude 2’s complement representation exponent + bias mantissaexponents (significand)

IEEE Standard 32-bit Floating-point Representation 1 8 bits 23 bits Bias is 2 k-1 -1= 127 The leftmost 1 in fraction is implied. biased exp. fractions

IEEE Standard 32-bit Floating-point Representation 1 8 bits 23 bits Bias is 2 k-1 -1= 127 The leftmost 1 in fraction is implied. biased exp. fractions TypeSign Actual Exponent Exp (biased) Exponent fieldSignificand (fraction field)Value Zero 0− Negative zero 1− −0.0 One Minus One −1.0 Smallest normalized number *− ±2 −126 ≈ ±1.18×10 −38 Largest normalized number * ±(2−2 −23 ) × ≈ ±3.4×10 38 Positive infinity ∞ Negative infinity −∞ Not a number * non zeroNaN * Sign bit can be either 0 or 1.

Floating-point Addition/Subtraction Algorithm Ex: using 4-bit registers X = = x 2 4+b Y = 1.1 = 0.11 x 2 1+b = x 2 4+b S significand exponent X Y Z Z= b b b0

Floating-point Multiplication Algorithm Ex: using 4-bit registers X = = x 2 4+b Y = 1.1 = 0.11 x 2 1+b Add exponents and subtract bias: ((4+b) + (1+b)) – b = 5+b Z= x 2 5+b = x 2 4+b

Floating-point Division Algorithm Ex: using 4-bit registers X = = x 2 4+b Y = 10.0 = 0.10 x 2 2+b Subtract exponents and add bias: ((4+b) - (2+b)) + b = 2+b Z= x 2 2+b