Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 An ASIC for timing adjustment in LHC CERN PH/MIC, Geneva Switzerland H. Furtado, A. Marchioro, P. Moreira and J. Schrader

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Outline Motivation ASIC Functionality and Architecture Measurements and results

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Objectives Timing Adjustment Self-Calibrated Radiation Tolerant

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Features 4 channel programmable CMOS delay line –Master channel: Calibration reference Clock signal Clock frequencies: –32, 40, 64 or 80 MHz –4 channels: (Non-)periodic digital signals Independently programmed –Channel phase: 0.5 ns resolution –I2C interface: ASIC control

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Features –0.25 µm CMOS technology –Radiation tolerant –Self calibrating –Phase resolution: 0.5 ns –Output jitter: < 19 ps (rms) –Integral non-linearity < 44 ps (rms) –Differential non-linearity < 35 ps (rms) –Configurable I/O: CMOS 2.5V LVDS –Supply voltage: 2.5 V –Package: TQFP32 –Power Consumption of 130 mW

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Layout

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Architecture

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC DLL Architecture

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Speeding up and Slowing Down

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Replica Channels

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Getting the Delayed Signal

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Different Input Reference Frequencies

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Measurements -40MHz and at room temperature Functionality Integral and Differential Non-Linearity Jitter Crosstalk

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Functionality - CLK CMOSLVDS

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error - CLK CMOSLVDS Integral error rms: 41ps ; p-p: ±79ps Integral error rms: 41ps ; p-p: ±71ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error - CLK CMOSLVDS Differential error rms: 35ps ; p-p: ±100ps Differential error rms: 32ps ; p-p: ±84ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error : CH0 (LVDS) CLK CH0 Integral error rms: 43ps ; p-p: ±87ps Integral error rms: 41ps ; p-p: ±71ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error : CH0 (LVDS) CLKCH0 Differential error rms: 31ps ; p-p: ±84ps Differential error rms: 32ps ; p-p: ±84ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Pulse Width CH0: blue - rising edge, red – falling edgeCH0: measured width

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter - CLK (CMOS) std dev = 15ps 40MHz clock - TAP 50

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter - CLK (LVDS) std dev = 15ps 40MHz clock - TAP 50 Gen: 8 ns

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter – CH0 (LVDS) std dev = 18ps 40MHz clock - TAP 50 Gen: 8 ns

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Influence of crosstalk on Jitter Input signal correlated with the clock std dev = 18ps 40MHz clock - CH0 - TAP 50 Gen: 8 ns

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Influence of crosstalk on Jitter std dev = 19ps Input signal not correlated with the clock 40MHz clock - CH0 - TAP 50 Gen: 8 ns

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error: Crosstalk CH0 (w/crosstalk from CH1 - correlated) Integral error - Correlated crosstalk rms:42ps ; p-p: ±70ps Integral error - Clk no crosstalk rms: 41ps ; p-p: ±71ps Integral error - CH0 no crosstalk rms: 41ps ; p-p: ±71ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error: Crosstalk CH0 (w/crosstalk from CH1 - correlated) Differential error - Correlated Crosstalk rms: 32ps ; p-p: ±83ps Differential error - Clk rms: 32ps ; p-p: ±84ps Differential error – CH0 w/o crosstalk rms: 31ps ; p-p: ±84ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error: Crosstalk CH0 (w/crosstalk from CH1 - not correlated) Integral error - Non Correlated Crosstalk rms43ps ; p-p: ±75ps Integral error - Clk rms: 41ps ; p-p: ±71ps Integral error – CH0 w/o crosstalk rms: 41ps ; p-p: ±71ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error: Crosstalk CH0 (w/crosstalk from CH1 – not correlated) Differential error - Non Correlated Crosstalk rms: 34ps ; p-p: ±87ps Differential error - Clk rms: 32ps ; p-p: ±84ps Differential error – CH0 w/o crosstalk rms: 31ps ; p-p: ±84ps

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Electrical Characteristics Power Consumption: 130 mW Lock range in the 40 MHz mode: MHz Supply Voltage Range: V

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Conclusions -The Delay 25 has been fabricated in the 0.25 µm CMOS technology -Self calibrating -Independently programmable 4 channel with 0.5ns resolution -Performance has been evaluated -Correct functional behaviour -Jitter < 19 ps (rms) -Integral Error < 44 ps (rms) -Differential Error < 35 ps (rms) -Power Consumption: 130 mW -Cost ~10 CHF -More Tests Scheduled -Characterization at all frequencies -Radiation