Plastic Packages 100/128/144 pins TQFP (Thin Quad Flat Package)-Thin Quad Flat Package 144 pin BGA (Ball Grid Array)

Input Output Ports Timer Host Ports External Ports Link Ports Input Output Ports Timer Host Ports External Ports Link Ports Compute Engine Data Memory Data Memory Program Memory Program Memory I/O Connects to Outside World What’s Inside DSP (Elements of DSP)

Program Memory: – Stores the programs the DSP will use to process data Data Memory: – Stores the information to be processed Compute Engine: – Performs the math processing, accessing the program from the Program Memory and the data from the Data Memory Input / Output: – Serves a range of functions to connect to the outside world

Types of Architecture Von Neumann Architecture Harvard Architecture Super/ Modified Harvard Architecture

Von Neumann Architecture Memory Instruction & Data CPU Address Bus Data Bus

Harvard Architecture Program Memory CPU Address Bus Data Bus Data Memory Address Bus Data Bus

Uses an advanced, Modified Harvard architecture Maximizes processing power by providing TMS32054XX 4 pairs Bus Structure 3 Pairs Data Memory 1 Pair Program Memory

PB : Program Bus PAB : Program Address Bus Program Memory bus to read OPCODE & Immediate Operand CB : C Bus CAB : C Address Bus DB : D Bus DAB: D Address Bus Data Memory Buses To Read data simult. From memory EB : E Bus EAB : E Address Bus Data Memory bus to Write Data in Data Memory

Features of TMS32054XX 16 bit CPU Can execute 40 to 120 Million Instructions Per Second 17×17 bit MAC 64k × 16 bit physical program memory address space 64k × 16 bit external data memory address space 64k × 16 bit external IO address space Programmable timer & PLL DMA interface 100/128/144 TQFP & BGA packages

Instruction Pipelining in TMS320C54X Processors 3.Decode The opcode is decoded to determiine access operation 2. Program Fetch The op-code is fetched from PB & loaded into Instruction Register 1.Program Pre fetch PAB is loaded with the address next instruction to be fetched

6.Execute Perform the task specified by the instruction 5. Read The operands are read from the buses DB & CB 4.Access Operand address is loaded on data DAB – Data Address Bus. If 2 nd operand is required, then another address is loaded into CAB

Sr no Parameter DSP ProcessorGPP Processor 1 Instruction CycleSingle Cycle ( i.e., true instruction cycle) Multiple instruction cycle for one instruction 2 Instruction ExecutionParallel execution is possibleAlways sequential execution is possible 3 Operand fetched from memory Multiple operands are fetch simultaneouslyOperands are fetch sequentially 4 MemoriesSeprate program memory and data memory Normally no such separate memories are present 5 On-chip/off-chip memories Program memory and data memory are present on- chip and expandable off-chip. Normally on-chip cache memory is present.Main memory is off-chip. 6 Address genration Addresses are generated combinely by DAGs and program sequencer. Program counter is incremented sequentially to generate addresses. 7 Address/data bus multiplexing Address and data buses are not multiplexed. They are separate on chip as well as off chip. Address/data buses can be separate on the chip but usually multiplexed off-chip. 8 Computational units Three separate computational units: ALU,MAC and shifter. ALU is the main computational unit. 9 Suitable forArray processing operationsGenral purpose processing 10 Queuing/PipeliningQueuing is implemented through instruction register and instruction cache Queuing is performed explicitly by queuing register for pipelining of instructions