Ground Planes, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.

Slides:



Advertisements
Similar presentations
1 Designing for DVI General Applications Considerations.
Advertisements

Chapter 13 Transmission Lines
On-chip inductance and coupling Zeynep Dilli, Neil Goldsman Thanks to Todd Firestone and John Rodgers for providing the laboratory equipment and expertise.
   >>> 
Here’s a partial schematic we’ll use to illustrate the advantage of a ground plane. The idea is that an output pin on the microprocessor is driving an.
The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic.
EELE 461/561 – Digital System Design Module #6 Page 1 EELE 461/561 – Digital System Design Module #6 – Differential Signaling Topics 1.Differential and.
Lecture 24: Interconnect parasitics
MB4 New compared with MB3: Digital drivers / transformer drivers options 14 OPAMPS instead of 4 Thinner coaxial cables Shorter umbilical Heater coil integrated.
ECE 404 PCB Design Presentation Jakia Afruz.  Printed Circuit Board  Electronic Board that connects circuit components  PCB populated with electronic.
PCB Design & Layout Tips
Layout Considerations of Non-Isolated Switching Mode Power Supply
Ground and Power Planes
A look at “Common” mistakes
Module 5: Advanced Transmission Lines Topic 3: Crosstalk
A look at “Common” mistakes David Green Oklahoma State University
PCB Layout Introduction
1 Induction Motors ©Dr. B. C. Paul The Induction Motor Most motors have a problem in that the rotor moves To run a current to it and create an.
Modelling of TPM noise problems Greg, following discussions and measurements with David and Senerath.
Transmission Line “Definition” General transmission line: a closed system in which power is transmitted from a source to a destination Our class: only.
PCB Layout Introduction
Crosstalk Crosstalk is the electromagnetic coupling between conductors that are close to each other. Crosstalk is an EMC concern because it deals with.
READING QUIZ False True
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.
IPC Power Distribution Considerations A predominately important factor that should be considered in the design of a printed board is power distribution.
Shielded Wires Let us say that the voltages measured at the terminal of the receptor circuit are beyond the desired level. What can we do? Two common solutions.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 19, 2010 Crosstalk.
11/22/2004EE 42 fall 2004 lecture 351 Lecture #35: data transfer Last lecture: –Communications synchronous / asynchronous –Buses This lecture –Transmission.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk.
1 Interconnect/Via. 2 Delay of Devices and Interconnect.
Global Circuit Page 1  Basic Design Rule for Advanced PCB (1) 1. High speed current path Load Driving gate Current trace At low frequency current, follows.
1 Decoupling Capacitors Requirements Intel - Microprocessor power levels in the past have increased exponentially, which has led to increased complexity.
EECS 713 Project Instructor: Prof. Allen Presented by: Chen Jia.
Magnetism Unit 12. Magnets Magnet – a material in which the spinning electrons of its atom are aligned with one another Magnet – a material in which the.
PCB DESIGN Dr. P. C. Pandey EE Dept, IIT Bombay Rev. Jan’16.
Chapter 4: Secs ; Chapter 5: pp
Inductance Screening and Inductance Matrix Sparsification 1.
Chapter 2. High-speed properties of logic gates.
전자파 연구실 1. Fundamentals. 전자파 연구실 1.1 Frequency and time Passive circuit elements is emphasized in high speed digital design : Wires, PCB, IC- package.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 21, 2012 Crosstalk.
Transform your ideas into products 1 High Speed Design Basic ㈜ 에이로직스 성남시 분당구 야탑동 성원프라자 402호 전화 : 팩스 :
Noise & Grounding Andrei Nomerotski (U.Oxford) 17 July 2007.
전자파 연구실 1 5. Ground planes and layer stacking. 전자파 연구실 2 Provide stable reference voltages for exchanging digital signals Distribute power to all logic.
Piero Belforte, HDT 1999: PRESTO POWER by Alessandro Arnulfo.
CROSSTALK, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
Digital Signal Model Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology
Non Ideal Behavior of Components, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology NIB_2 Course outline.
Power Distribution Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
TERMINATIONS Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
HDT, 1998: Resistance, Inductance, Capacitance, Conductance per Unit Length Lossless case.
Piero Belforte, HDT, July 2000: MERITA Methodology to Evaluate Radiation in Information Technology Application, methodologies and software solutions by Carla Giachino,
Adapter Board Design Changes
High-Speed Serial Link Layout Recommendations –
How to debug PMP systems A guideline for Application Engineers
Eddy Current A current induced in a solid conducting object, due to motion of the object in an external magnetic field. The presence of eddy current in.
Faraday’s Law (Induced emf)
PCB Design & Layout Tips
Electromagnetic Compatibility BHUKYA RAMESH NAIK 1.
Richard J. Mohr President, R. J. Mohr Associates, Inc.
Day 33: November 19, 2014 Crosstalk
Open book, open notes, bring a calculator
Magnetostatics.
High-Speed Serial Link Layout Recommendations –
Day 31: November 23, 2011 Crosstalk
Inductance Screening and Inductance Matrix Sparsification
Lattice (bounce) diagram
SAS-3 12G Connector Drive Power Pin Configuration
Ground and Power Planes
Presentation transcript:

Ground Planes

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_2 Course outline Contents Digital Signal Model Non Ideal Behavior of Components High Speed Properties of Digital Gates Ground PlanesGround Planes Crosstalk Power Distribution Terminations Low frequency High frequency Current distribution Inductive crosstalk Slots in ground plane Additional inductance Two traces over a slot “Cross-finger” layout Advantages & disadvantages “Finger” layout Advantages & disadvantages Guard traces Use of guard traces Current paths Ground planes properties

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_3 Low frequency In solid ground planes, at low frequencies, return currents follow path of least resistance (minimum distance) Signal trace Return path Ground plane

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_4 High frequency In solid ground planes, at high frequencies, return currents follow a path of least inductance (minimum area) Signal trace Return path Ground plane

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_5 Current distribution At high frequencies (typical digital circuits), return currents tend to stay near the signal trace, with a distribution in the cross-section given by: I 0 : total trace current 0 y w h Ground plane Signal current density

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_6 Current distribution The current distribution in the cross-section influences other adjacent traces 0 y w h Ground plane  v I0I0 Inductive crosstalk Current distribution I(y) Magnetic flux  Induced voltage v

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_7 Inductive crosstalk Inductive crosstalk depends on: –separation between traces according to the law –time derivative of the signal: –longitudinal length along which the traces run parallel higher crosstalk for short rise times or high frequencies

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_8 Slots in ground plane In presence of a slot in ground plane: –return current cannot stay under signal trace: loop increased inductance Signal trace Return path Ground plane with a slot

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_9 Additional inductance Additional inductance for the trace: Width q of the slot has almost no influence; in fact D is responsible for current diversion: –thin or large slots of same length have the same effect Slots towards one end of the trace have less effect Slot in ground plane Signal trace D q w

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_10 Additional inductance Excess inductance due to slots slows down signal edges (increase of rise time)  SIGNAL Z0Z0 Z0Z0 L Rise time introduced by the additional inductance Total rise time of the received signal

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_11 Additional inductance Excess inductance due to slots in lines with capacitive loads may cause problems on resonant behavior of circuits L RSRS C LOAD If Q > 1, the circuit rings If Q  1, the circuit response is damped with a rise time

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_12 Two traces over a slot Strong overlap of return currents of the two traces –large mutual inductance –large crosstalk Ground plane with slot Signal trace 2 Return current of trace #1 Return current of trace #2 Signal trace 1

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_13 Two traces over a slot High coupling for very close traces (d  D/2) Crosstalk depend on: –L M –time derivative of signal –coupling length Signal trace #2 Slot in ground plane Signal trace #1 D q w d Mutual inductance

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_14 “Cross-finger” layout Ground and power distribution are non-solid. They are connected at crossings by bypass capacitors Top layer (+V CC ) Bottom layer (ground) Signal trace Return current path

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_15 Advantages & disadvantages Solution’s advantages –double face layout only Solution’s disadvantages –inductance of the signal line is larger than for solid ground and power planes This solution is the best compromise that avoids solid copper planes

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_16 “Finger” layout “Finger” layout is another configuration with non- solid power and ground planes Top layer (+V CC ) Bottom layer (ground) Signal trace Return current path

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_17 Advantages and disadvantages Advantages –double face layout only Disadvantages –higher inductance of the signal line (larger also than “cross-finger” layout) Rule –due to high inductance, avoid this layout for high speed logic

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_18 Guard traces Without guard trace G, crosstalk level in #2 due to a signal in #1 is proportional to 0 y #1 h Ground plane G#2 #1 #2 G GND

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_19 Use of guard traces With guard trace, grounded on both sides, crosstalk level is divided by 2 Since acceptable crosstalk level is  1% of interfering signal, guard traces are seldom needed. In most cases it’s sufficient to separate the traces u.l. = unit length (y/h = 10)  crosstalk <1% In general, no need for center guard trace 4 u.l. 1 u.l. Ground plane

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_20 Current paths All currents must return to their source V CC GND This configuration is enough for functionality but it’s BAD for EMC point of view (large loops  radiation)

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_21 Current paths This configuration is GOOD for both functionality and EMC point of view V CC GND Always control current return paths

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_22 Ground planes properties Best way to control high speed return currents is to use PCBs with copper planes: –best zero (ground) reference voltage –radiated emissions are reduced by dB Rule of thumb –clock speed > 5 MHz –rise times < 5 ns Use multilayer with power and ground plane

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_23 Next topic Crosstalk