MERITA

© Bull 1999 Merita SYSTEM DESCRIPTION QUADRIPROCESSOR SERVER  IBM microprocessor North-Star  power PC architecture  260 MHz internal clock  64 Mbyte L2 Cache memory  130 MHz bus  ASIC Chip Set designed by Bull  7 PCI slots.

© Bull 1999 Merita SYSTEM

© Bull 1999 Merita CPU board  1 IBM Power PC Microprocessor: Northstar  10 L2 Cache SRAMs  Northstar and SRAMs decoupling capacitors  Up to 540 MHz internal Microproc. frequency  Up to 270 MHz Cache bus frequency  22 layers board (Z0  54 , tpd  0.07ns/m)  Pure symmetric stripline structure

© Bull 1999 Merita CPU board

© Bull 1999 Merita Board Design flow : Postlayout S.I.analysis Board specs Board design Prelayout S.I.analysis yes no Board routing yes no Board construction Board testing

© Bull 1999 Merita CPU board stack-up

© Bull 1999 Merita OPEN ISSUES PROCESSOR EVOLUTION High internal frequency (up to 520 MHz) High power currents  30 W with 2.5 V (1.8 in future) INCREASE OF THE NOISE PROBLEMS: Ground bouncing Irradiated noise Filtering rules The Methodology still applied does not allows any evaluation of power noise nor at prelayout neither at post layout levels

© Bull 1999 Merita SOLUTION AVAILABILITY OF A SIMULATION TOOL ABLE TO EVALUATE THE POWER PLANE CURRENT BEHAVIOUR

© Bull 1999 Merita MEASURES Near field measures on the CPU board. HW SET UP –Open System –Close field probe HP11940A –Spectrum analyser Tektronix 496 –Probe on the back of Microprocessor die

© Bull 1999 Merita MEASURES SW SET UP  Processor running 2 different test: To maximise the microprocessor activities To maximise the Cache activities  System at 4 different system clock frequency: 36, 40 and 43.5 MHz  Microprocessor internal frequency ratio: 6/1 and 8/1 (from 198MHz to 320 MHz)  Cache frequency ratio: Half the microprocessor frequency

© Bull 1999 Merita MEASURES RESULTS : Running the “CPU TEST” the processor emission is made by several harmonic of the clock frequency according to the rule: f = n * f clk *R/3 R = Processor internal freq./ bus freq. Running the “ CACHE TEST” the processor emission is made only by the harmonic of the cache bus frequency (half of processor internal frequency)

© Bull 1999 Merita MEASURES

© Bull 1999 Merita MEASURES

© Bull 1999 Merita MEASURES Analysis methodology  Problem –the processor power current wave form is not known  Assumptions –for each clock harmonic the emission amplitude is the same at the different clock ratios –by comparison of these amplitudes it is possible to build a qualitative description of frequency behaviour of the board and processor

© Bull 1999 Merita SIMULATION RESULTS

© Bull 1999 Merita MEASURES

© Bull 1999 Merita MEASURES

© Bull 1999 Merita MEASURES Results –the sets of different harmonics show a qualitative good trend –the trend of board frequencies looks similar to the simulated ones

© Bull 1999 Merita Board Design flow using HDT tools: Postlayout S.I.analysis Boardspecs Board design Prelayout S.I.analysis yes no Boardrouting yes no Boardconstruction Boardtesting Boardfiltering designwih PRESTO yes no Board EMI analysis yes no