21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com Home Spicy SWAN Design Report

21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com * 2014­12­08­03­58­54 ******************HEAD********************* *SWAN/DWS Netlist and simulation file *Copyright 1985­2015 Piero Belforte and Giancarlo Guaschino *Generated by: SPICY SWAN (ischematics.com) *File: SPA_DIFF_COUPL_FREQ8 ****************************************** *Author: pierobelforte *Date: Dec *Desc: FREQUENCY RESPONSE OF *DIFFERENTIAL 60CM 100 OHM *STRIPLINE MODELED AS *ONE BTM PWL BLOCK. ******************ENDHEAD****************** *CKT START V PULSE(0 20GIG 0us 200us) X PEAK_DETECT X PHASE_METER_180 R X VFREQ_SWEEP_50_SOFT R X4 7 8 PEAK_DETECT X PHASE_METER_180 E_DIFF N X VFREQ_SWEEP_50_SOFT R X DIFF_STRIPLINE_60CM_SPAR_CORR * {RS} N_8=1 N_9=2 N_S21_AMPLITUDE=3 N_6=4 N_4=5 UN_13=6 UN_10=7 N_S11_AMPLITUDE=8 UN_15=9 N_S21_PH ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File * *Author: pierobelforte * Date: Sat 12 Apr :34:37 GMT *Notes: ********************** * * {RS} N_IN=2 UN_3=3 N_OUT=4 N_3=5.SUBCKT PEAK_DETECT 2 4 E P0 3 4 ­ GIG *TAU=500ns C p R K ****************************************** *MODELS USED IN CIRCUIT ******************************************.ENDS ********************** *Spicy SWAN ­ SWAN Model File * *Author: Piero Belforte * Date: 14 June :42:04 GMT *Notes: 0 to +­180 degrees *PHASE METER *IN THRESHOLD SET * TO 1e­12V. *START­STOP *IMPLEMENTATION. *IN THRESHOLD SET * TO 1e­12V. ********************** * * {RS} UN_18=2 UN_12=3 UN_13=4 UN_10=5 UN_11=6 UN_17=7 UN_14=8 UN_15=9 N_IN1=10 N_IN2=11 N_GEN=12.SUBCKT PHASE_METER_ * IN1 IN2 OUT E THR(1E­12 0 1) 0N 1 R K C n E__ PWL( ­ ) E THR(1E­12 0 1) 0N 1 E_DEL F X SLOGIC_RSFF E_DEL F E THR(1E­12 0 1) 0N 1 E THR(1E­12 0 1) 0N 1 E_DEL F E_DEL F ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File

21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com * *Author: pierobelforte * Date: Fri 16 May :13:53 GMT *Notes: ********************** ** {RS} N_OUT=1 ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File * *Author: Piero Belforte * Date: Fri 16 May :09:21 GMT **********************.SUBCKT SLOGIC_RSFF *SET=2 RESET=11 Q=5 Q_BAR=10 ****************************************** *Author: Piero Belforte *Date: Wed Mar *Desc: SR Flip Flop implemented by 2 *2­INPUT Ideal NOR GATES ****************************************** V0 8 0 DC(1) R THR( GIG) R THR( GIG) R V3 3 0 DC(1) R THR( GIG) R THR( GIG) R ENDS SLOGIC_RSFF.ENDS PHASE_METER_180 ********************** *Spicy SWAN ­ Model File * *Author: Piero Belforte * Date: Tue 05 Nov :08:40 GMT **********************.SUBCKT VFREQ_SWEEP_50_SOFT ** F_IN=10 OUT=20 VREF=21 *VOLTAGE SWEPT FREQ: EHALF VF 40 0 SIN( 0 2V V(30) ) RF *modulating out voltage (soft start,50ns) EF * 50 1 *soft start (100ns) VSOFT_START 50 0 PULSE( 0 1 0ns 100ns).ENDS VFREQ_SWEEP_50_SOFT ********************** *Spicy SWAN ­ Model File * *Author: pierobelforte * Date: Sun 07 Dec :16:55 GMT **********************.SUBCKT DIFF_STRIPLINE_60CM_SPAR_CORR 1 2 *IN OUT *DIFFERENTIAL MODE PWL MODEL FROM ZYT200 VF MODEL B_60CM_STRIPLINE_PWL S11=PWL( ns ­ ns ­ ns ­ ns ns ns ns ns ns ns ns ns ns ns ns NS NS NS NS NS NS NS NS NS.0275) + Z0=100 TD=0n + S21=PWL( + 0ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ns ns ns ns ns ns ns ns ns NS NS NS NS NS NS NS NS.975) Z0=100 TD=3.75n.ENDS DIFF_STRIPLINE_60CM_SPAR_CORR *CKT END ****************************************** *Simulations *Note: This portion below is updated when you simulate ******************************************.OPTIONS DELAYMETH=INTERPOLATION

21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com Copyright © 2011­2015 iSchematics LLC [circuit, simulation, simulator, ipad, ios, schematics, schematic, pspice for ipad, spice for ipad, spice for ios, schematic capture, circuit design, circuit design on ipad, circuit design for ipad, circuit simulation, circuit simulation for ipad, circuit simulation on ipad, electronics, electronic, Spicy Schematics, tablet, tablets, mobile, touch, ipad circuit simulator] iPhone and iPad are trademarks of Apple Inc..TEMP 27.TRAN TSTEP=5e­12 TSTOP=200e­6 TSTART=1e­6 LIMPTS=5000 V(17) V(3) V(10) V(8) V(19).END