1 IBIS Standard Integrated Circuits Modeling Service based on ATE Equipment Family Schlumberger ITS9000 July 6, 2000 CSELT P.Belforte - M.Gandini - G.Ghigo - F. Maggioni -

2 Signal Integrity Simulation on PCB Signal integrity simulation is now a normal pre/post layout analysis for big/medium PCB’s manufacturers Fast rise/fall times High bit-rates EMC constraints “Signal integrity” driven router Electrical simulation of interconnection on PCB

3 Signal Integrity Models Macromodeling (i.e. based on IBIS standard) allows the simulation of all interconnections of a PCB in a single run * Spice model disadvantages Macromodel advantages Propagation, Losses, Crosstalk, Ground bounce simulation accuracy depends on the driver/receiver model accuracy Slow, convergence problems, no possible to use in simulations of large circuits, Spice problems with transmission line simulations, proprietary information on process and topologies Fast, easy to understand, portable, no proprietary information on process and topologies, match transmission line simulators characteristics, easy to extract from measurements. * For example: ground plane noise evaluation due to simultaneous switching noise

4 Standard IBIS 1)Component pinout description (i.e. the assignment “pin_number” – “driver/receiver_type”); 2)I/O capacitance description, static characteristics and rise/fall time (driver side only) of different driver/receiver defined in the first section. Electrical Level Simulation need Models Interchange IBIS Format IBIS (I/O Buffer Information Specification) Standard describes a behavioural model of the I/O section of digital integrated circuits with the purpose of doing accurate signal integrity simulations of the printed circuit board or MCM that uses the digital integrated circuit itself. The description of a component is composed of two sections:

5 Data Sources IBIS behavioral models can be extracted from: datasheet: insufficient information -> unreliable models Spice simulation of driver/receiver -> accurate enough, process corners availability measurements -> very accurate and “fitted” on the lot, include also package. IBIS models availability from measurements represents a big added value for the final user.

6 CSELT IBIS model usage experiences 1) Signal Integrity simulation is necessary to design a PCB critical section (clock distribution, fast bus, connectors pin mapping, digital noise on “sensitive” analog interconnections, etc.) 2) Poor quality for models available on WEB - wrong data (static characteristics, rise/fall times, capacitances) - incomplete data - “ghost” clamping diode - 30A clamping currents - … The final user spends lot of time to check the IBIS model: if the application is critical, the trend is to characterize the component with measurements in order to increase the WEB IBIS model confidence.

7 IBIS Models Availability on WEB IDT: ALVC, LVC, SRAMs FIFOs, etc. TI:GTL, LVC, FB, SSTL, LVDS, LVCH, etc. NATIONAL:Clock gen., DRAM contr., GTL, RS422 drivers, LVDS, etc. CYPRESS:SRAMs, Clock buffer, FIFOs, HotLink, PLD, etc. MOTOROLA:POWERPC, SRAM, etc. XILINX:Spartan, Virtex, Virtex-E, XC3000, XC4000, etc. ST: FLASH WEB IBIS models search* results: * 15’ search time for each vendor The number of designers that address the technical procurements on “IBIS models availability” basis is increasing.

8 IBIS Modeling Service CSELT has developed a methodology* of IBIS models extraction using the ATE equipment ITS 9000 that allows the characterization of all pins of the component. * patent pending Standard circuits IBIS models. ASICs IBIS models.

9 Standard IC and ASICs IBIS Models Allows the extraction of IBIS models with typical, min and max parameters. Allows parameters’ periodical monitoring & quality verification Accurate modeling for ASICS I/O cells

10 Modeling from Measurements Verification/extraction of parasitic effects (capacitance, package) to be included in the Spice-derived models Improve models extracted from Spice simulations available in WEB site. Strong “psychological effect” on customers because “guarantee” and validate Spice-derived IBIS models. Possibility to obtain IBIS models for each lot of components easily. Strong request from the market. Imagine, marketing and business opportunity (modeling on demand)

11 Proposal Collaboration (i.e.: to adapt modeling methodology on Schlumberger equipment) Additional CSELT services: IBIS modeling service (board test preparation, test pattern, measurements, data post-processing and documentation) Technical consulting on IBIS modeling, signal integrity and EMC issues

12 Supplemental Analysis The methodology is open to the IBIS format evolution: Clamp diodes transit time evaluation (IBIS rel 3.2). Noise created by simultaneous switching, Package modeling, Programmable buffer

13 Data Preparation and Setup Component datasheet analysis (pin number, package, JTAG/noJTAG, etc.). Test Board:

14 Component Measurements Test Pattern generation –different for JTAG/nonJTAG components Measurements –I/O static characteristics (V/I) pull-up, pull-down, clamp diodes –Drivers waveforms rise and fall time –I/O scattering measurements input/output capacitance, clamp diodes transit time (IBIS 3.2) Note: JTAG is a standard that adds some pins dedicated to the test of the component. With these pins it is possible to isolate I/O drivers and receivers from the core logic and control them independently.

15 IBIS Model Extraction (1) Input/Output classification –Static characteristics are organized by class. –For each class a typical characteristic is extracted. –Min/Max characteristic could be extracted as option. The graph shows 5 output class identification.

16 IBIS Model Extraction (2) The measurement of the real waveform of the driver, requires a special optimization procedure by an electrical simulator (Spice, …) Measured parameterRequired parameter DUT ATE (DSO) Measurement setup (transmission lines, discontinuities, loss) DUT DSO t (ns) V Real Parameter Extraction

17 IBIS Model Extraction (3) Real Waveform The extrapolation of the waveform is done in particular load conditions. The IBIS standard specifies 50ohm as default (very good for measurements comparison), but a load >1Kohm is more useful to build up macromodels based on Thevenin architecture.

18 IBIS Model Extraction (4) I/O Capacitance ATE equipment is used as a time domain reflectometer (TDR). Comparison between simulated and measured reflected waveform. Measurement Setup

19 IBIS File Preparation The preparation of the IBIS file is done by organizing all formerly extracted parameters (most of them are V/I or V/t characteristics) in a particular textual format. The description of a component in a IBIS 2.1 format is composed by two sections: The first section describes the component pinout (i.e. the assignment “pin_number” - “driver/receiver_type”). The second section describes the input/output capacitance, the static characteristics and the rise/fall time of the drivers/receivers defined in the first section. Operations are the following: Pinout description. Drivers/Receivers description. Model validation: syntactical and functional model verification. Report layout and archiving.

20 Further Analysis The methodology that uses the Schlumberger ATE ITS9000 allows further and detailed analysis like: Clamp diodes recovery time (IBIS 3.2). Dynamic behaviuor of clamp diodes. Simultaneous switching noise analysis. The test board could also be used by external equipments with higher measurement bandwidth to extract other interesting parameters like, for instance, a package model.

21 More Info, Links More info on CSELT labs could be found on our official WEB site For more info on our Debugging and Testing lab, please visit our site: or go directly to the IBIS pages: