1 Control Unit SC 15 I Memory PC OPR q0 q7 AC t0 t1 t2 FGO t3

Slides:



Advertisements
Similar presentations
BASIC COMPUTER ORGANIZATION AND DESIGN
Advertisements

Boolean Algebra Variables: only 2 values (0,1)
X March C- Copyright Soft Test Inc. Yellow Black = Stored data | Yellow = Write cycle | Red = Read cycle March C- Fundamentals of.
Game page Simplifying Solving Po Pourri
S0 S1 S2 S J Trellis Diagram.
Inside the binary adder. Electro-mechanical relay A solid state relay is a switch that is controlled by a current. When current flows from A to B, the.
REMOTE CONTROL OF DEVICES USING CELLPHONES
Basic Computer Organization
The Fetch – Execute Cycle
1 Linked List Demo Node third = new Node(); third.item = "Carol"; third.next = null; Node second = new Node(); second.item = "Bob"; second.next = third;
Error in synchronous Demodulator ระบบวิทยุ (Radio System) ผู้ช่วยศาสตราจารย์ธราดล โกมลมิศร์ ภาควิชาวิศวกรรมไฟฟ้า คณะวิศวกรรมศาสตร์ มหาวิทยาลัยเชียงใหม่
EX 6B THE RELATIONSHIP BETWEEN ARITHMETIC SEQUENCES AND FIRST ORDER DIFFERENCE EQUATIONS.
Princess Sumaya University
4.1 Powers of 10.
CS/COE1541: Introduction to Computer Architecture Datapath and Control Review Sangyeun Cho Computer Science Department University of Pittsburgh.
Datorteknik MainMemory bild 1 Memory The programmer’s model.text,.data –user program (instruction memory) and data area.ktext,.kdata –kernel program and.
CPS-509 COMPUTER ORGANIZATION & ARCHITECTURE
Target code Generation Made by – Siddharth Rakesh 11CS30036 Date – 12/11/2013.
Central Processing Unit
CS364 CH16 Control Unit Operation
M. Mateen Yaqoob The University of Lahore Spring 2014.
Damian BrowneLuis PabonPedro Tovar The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine.
ARITHMETIC LOGIC SHIFT UNIT
CPS 101 Introduction to Computational Science Wensheng Shen Department of Computational Science SUNY Brockport.
Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction.
Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009
Chapter No 5 Basic Computer Organization And Design.
1 Basic Computer Organization & Design Computer Organization Computer Architectures Lab BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer.
Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.
Bus Architecture Memory unit AR PC DR E ALU AC INPR 16-bit Bus IR TR
Exam2 Review Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009.
The structure COMPUTER ARCHITECTURE – The elementary educational computer.
1 Purpose of This Chapter In this chapter we introduce a basic computer and show how its operation can be specified with register transfer statements.
M. Mateen Yaqoob The University of Lahore Spring 2014.
Lec 5 Basic Computer Organization
Fetch-execute cycle.
Fetch-Execute Cycle Fetch the next instruction Decode Execute It.
Dale & Lewis Chapter 5 Computing components
1 Basic Computer Organization & Design Computer Organization Prof. H. Yoon BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers.
Instruction.
Ch5. 기본 컴퓨터의 구조와 설계.
Interrupt Driven I/O on the Mano CPU Doing things decently and in order.
Bus Architecture Memory unit AR PC DR E ALU AC INPR 16-bit Bus IR TR
COMMON BUS SYSTEM Registers The registers in the Basic Computer are connected using a bus This gives a savings in circuitry over complete connections between.
Basic Computer Organization - Part 2 Designing your first computer
1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference.
Chapter 5 Computer Organization TIT 304/TCS 303. Purpose of This Chapter In this chapter we introduce a basic computer and show how its operation can.
UNIT 2 REGISTER TRANSFER AND MICROOPERATIONS
Symbol Hex Code Description I=0 I=1
Micro-Operations A computer executes a program Fetch/execute cycle
William Stallings Computer Organization and Architecture
BASIC COMPUTER ORGANIZATION AND DESIGN
Overview Instruction Codes Computer Registers Computer Instructions
BASIC COMPUTER ORGANIZATION AND DESIGN
The fetch-execute cycle
BASIC COMPUTER ORGANIZATION AND DESIGN
By: A. H. Abdul Hafez CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
سازمان و طراحي کامپيوتر پايه.
Computer Organization and ASSEMBLY LANGUAGE
Instruction and Control II
נושאי הפרק מבוא שפת מכונה שפת אסמבלר מעברים באסמבלר לולאות
Computer Architecture and Organization: L11: Design Control Lines
THE FETCH-EXECUTE CYCLE.
By: A. H. Abdul Hafez Computer Architecture and Organization: L06: Stored program and Instruction code.
PIPELINING Santosh Lakkaraju CS 147 Dr. Lee.
Computer Concept and Practice
Computer Architecture
Presentation transcript:

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

매크로 명령어 (=기계어, 어셈블리명령어) 처리 Fetch FR : 00 (C0) Execute FR : 10 (C2) Indirect FR : 01 (C1) Inturrupt FR : 11 (C3) c0t0 c0t1 c0t2 메모리 읽기 [ 명령어 읽기 : 메모리→CPU] - decode c1t0 c1t1 c1t2 c1t3 c3t0 c3t1 c3t2 c3t3 q7’Ic0t3 - branch [ 유효주소 만들기] ← 실행 명령 (ADD, AND) c2t0 c2t1 c2t2 c2t3 [ 실행 데이터 읽기] - no-op

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

매크로 명령어 (=기계어, 어셈블리명령어) 처리 Fetch FR : 00 (C0) Execute FR : 10 (C2) Indirect FR : 01 (C1) Inturrupt FR : 11 (C3) c0t0 c0t1 c0t2 메모리 읽기 [ 명령어 읽기 : 메모리→CPU] - decode c1t0 c1t1 c1t2 c1t3 c3t0 c3t1 c3t2 c3t3 q7’Ic0t3 - branch [ 유효주소 만들기] ← 실행 명령 (ADD, AND) c2t0 c2t1 c2t2 c2t3 [ 실행 데이터 읽기] - no-op

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

매크로 명령어 (=기계어, 어셈블리명령어) 처리 Fetch FR : 00 (C0) Execute FR : 10 (C2) Indirect FR : 01 (C1) Inturrupt FR : 11 (C3) c0t0 c0t1 c0t2 메모리 읽기 [ 명령어 읽기 : 메모리→CPU] - decode c1t0 c1t1 c1t2 c1t3 c3t0 c3t1 c3t2 c3t3 q7’Ic0t3 - branch [ 유효주소 만들기] ← 실행 명령 (ADD, AND) c2t0 c2t1 c2t2 c2t3 [ 실행 데이터 읽기] - no-op

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R

1 Control Unit SC 15 I Memory 14 12 PC OPR q0 q7 AC t0 t1 t2 FGO t3 4096*2bytes OPR 1 Control Unit M A q0 R 1 001 xxx 1 000 zzz yyy 100 100 3*8 decoder 101 xxx q7 yyy AC zzz t0 E 100 2*4 decoder t1 t2 FGI INPR OUTR FGO t3 MBR SC To I To OPR C0 C1 C2 C3 1 teletypewriter monitor 2*4 decoder To MAR S F R