LAB #5 Modular Design and Hierarchy using VHDL ENG2410 Digital Design LAB #5 Modular Design and Hierarchy using VHDL

Lab Objectives Understand the concept of modular design. Study the modular design flow using VHDL. Design adder/subtractor using modular design. Design a 7-segments decoder to activate the 7-segment displays available on the FPGA. Integrate the adder/subtractor and the 7-segment in one unit. ENG241/ Lab #5

Adder/Subtractor Design 4 bit adder/subtractor. Design 1-bit Full Adder The Full Adder is used to design 1-bit adder/subtractor. Using four 1-bit adder/subtractor to build the 4-bit adder/subtractor. ENG241/ Lab #5

4 Bit Adder/Subtractor ENG241/ Lab #5

7-Segments Display 7 LEDs form the display. Used to display numerical values. Some 7-Seg. Include extra LED for dots. ENG241/ Lab #5

7-Segment Decoder Take Binary number as Inputs. Generate the required bit string that display the numerical value on a 7-Seg Display. ENG241/ Lab #5

7-Segments on NEXYS 3 Board Four 7-Segments Displays Exist. The have common input. Transistors are connected to the Anode to select the required display. It is Active Low. ENG241/ Lab #5

Complete System Integrate the Adder/Subtractor and 7-Segments Decoder to form the complete system. Use the slide switches for data input. ENG241/ Lab #5

Sample Modular Design in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- This Code define XOR module entity xor_2 is port ( a,b : in std_logic; f : out std_logic); end xor_2; architecture dataflow of xor_2 is begin f <= a xor b; end dataflow; ENG241/ Lab #5

Sample Modular Design in VHDL Cont. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity parity_4 is port ( data : in std_logic_vector (3 downto 0); p : out std_logic); end parity_4; architecture structured of parity_4 is signal p_i : std_logic_vector (2 downto 0); --Signal Declaration component xor_2 --Component Declaration port ( a,b : in std_logic; f : out std_logic); end component; begin u1: xor_2 port map (data(0), data(1),p_i(0)); u2: xor_2 port map (p_i(0),data(2),p_i(1)); u3: xor_2 port map (f=>p_i(2),a=>data(3),b=>p_i(1)); p <= p_i(2); end structured; ENG241/ Lab #5

UCF File //Slide switches NET SW0 LOC = T10; NET SW1 LOC = T9; NET SW2 LOC = V9; NET SW3 LOC = M8; NET SW4 LOC = N8; NET SW5 LOC = U8; NET SW6 LOC = V8; NET SW7 LOC = T5; // Pushbutton switches NET BTNS LOC = B9; NET BTNU LOC =A8; NET BTNL LOC = C4; NET BTND LOC = C9; NET BTNR LOC = D9; // 7seg digit segments NET CA LOC = T17; NET CB LOC = T18; NET CC LOC = U17; NET CD LOC = U18; NET CE LOC = M14; NET CF LOC = N14; NET CG LOC = L14; NET DP LOC = M13; // 7seg selector transistors NET AN0 LOC = N16; //(LSD) NET AN1 LOC = N15; NET AN2 LOC = P18; NET AN3 LOC = P17; //(MSD) ENG241/ Lab #5

Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing codes or reports is NOT ALLOWED Copying reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it

Guidelines: Steps Build 7-seg decoder using VHDL (sample VHDL code is available) Create a symbol for the 7-seg decoder X3 X2 X1 X0 7-Seg Decoder a b c d e f g ENG241/ Lab #5

Guidelines: Steps Build (1-bit) HA using VHDL (code available) Build (1-bit) FA using VHDL, utilize the implemented HA (code available) Test the (1-bit) FA. ENG241/ Lab #5

VHDL CODE for 1-bit FA ENG241/ Lab #5

Guidelines: Steps Use 1-bit FA to build 4-bit adder using VHDL. Create a symbol for the 4-bit adder A3 A2 A1 A0 B3 B2 B1 B0 Cin 4-bit Adder Cout S3 S2 S1 S0 ENG241/ Lab #5

Guidelines: Steps Use Schematic capture to add XORs to change the adder to adder-subtractor. Interface the output of the 4-bit to the 7-Seg decoder. This should be done in one schematic file. ENG241/ Lab #5

Schematic ENG241/ Lab #5

Project Files HA – VHDL FA – VHDL 7-Seg Decoder – VHDL 4-bit Adder – VHDL 4-bit adder-subtractor – Schematic TOP Level is Schematic ENG241/ Lab #5