3/2/2017 Richard Kuo Assistant Professor MCU Overview 3/2/2017 Richard Kuo Assistant Professor

Outline What is a MCU ? Where are MCU used ? ARM Cortex-M series Brief Cortex-M0 Introduction

What’s the MCU ? A microcontroller is a single integrated circuit (IC) that contains a processor core, memory (SRAM, programmable ROM) and programmable input/output interfaces. MCU or uC is the abbreviation of the microcontroller. MCU are categorized in 3 groups by its data-bit width 8-bit 16-bit 32-bit

The basic components of a MCU A MCU consist of a processor core, memory and I/O interfaces CPU Flash ROM SRAM GPIO PWM Memory Interfaces AHB APB APB Bridge ADC I2C UART SPI

MPU vs MCU Microprocessor (MPU) Microcontroller (MCU) CPU >200MHz SRAM Cache DRAM SRAM CPU <200MHz ROM Flash ROM ADC SPI ADC SPI DAC UART DAC UART PWM USB PWM USB RTC CAN RTC CAN GPIO Ethernet GPIO Ethernet I2C HDMI I2C CPU core = ARM Cortex-A8/A9, ARM9/11 System has DRAM and runs OS ROM/Flash are out side of MPU chip CPU core = ARM Cortex-M0/M4 System has no DRAM and can’t run OS ROM is embedded in MCU chip

Broadcom Raspberry Pi 3 A 1.2GHz 64-bit quad-core ARMv8 CPU 802.11n Wireless LAN Bluetooth 4.1 Bluetooth Low Energy (BLE) 1GB RAM 4 USB ports 40 GPIO pins Full HDMI port Ethernet port Combined 3.5mm audio jack and composite video Camera interface (CSI) Display interface (DSI) Micro SD card slot (now push-pull rather than push-push) VideoCore IV 3D graphics core

Atmel Arduino UNO ATmega328 16-bit AVR CPU @16MHz 32KB Flash ROM (0.5KB used by bootloader) 2KB SRAM EEPROM 1KB 6 Analog I/O pins 20 Digital I/O pins (6 PWM pins) 40mA on I/O pins Board Input Voltage : 7~12V Chip Operating Voltage : 5V

Espressif ESP8266 32-bit Tensilica Xtensa LX106 RISC CPU @80MHz 64KB I-RAM & 96KB D-RAM External QSPI Flash 512KB ~ 4MB (up to 16MB) 802.11 b/g/n WiFi Support STA/AP/STA+AP modes Built-in TCP/IP protocol stack，support multiple TCP Client links Support Socket AT commands Support 16 GPIO pins (I2S with DMA) Support SPI, I2C Support UART interface Support one 10-bit ADC Support Smart Link networking Support OTA firmware upgrade Low Power operation 3.3V operating voltage 

MediaTek LinkIt Smart 7688 CPU is MIPS24KEc @580MHz I-Cache, D-Cache : 64KB, 32KB L2-Cache : N/A SPI Flash SD support SD-XC class10 SD support SD (Class 9) 1T1R 802.11n 2.4GHz DR-QFN156 (12mm x 12mm) PCIe x1 USB 2.0 x1 Fast Ethernet Switch 5 I2S x1 PCM x1 PWM x4 SPI x1 I2C x1 UART x3

Realtek Ameba RTL8195 ARM Cortex-M3 @166MHz 1MB ROM 2MB SDRAM (integrated) 512KB SRAM Integrated with 802.11 b/g/n 1x1 Wi-Fi NFC Tag with Read/Write Function 10/100 Ethernet MII/ RMII/RGMII Interface USB OTG- SDIO Device/SD card controller Hardware SSL engine Maximum 30 GPIOs 2 SPI Interfaces and support both master and slave mode 3 UART Interfaces including 2 HS-UART and one log UART 4 I2C Interfaces and support both master and slave mode 2 I2S/PCM Interfaces and support both master and slave mode 4 PWM interfaces- 2 ADC interfaces- 1 DAC interfaces

Microcontrollers Are Everywhere ! Where are MCU used ? Microcontrollers Are Everywhere !

ARM Cortex-M Family of 32-bit Processors (Courtesy of ARM)

Cortex-M Series CPU core Lowest Power and Area Cortex-M23 : TrustZone in smallest area, lowest power Cortex-M0+ : Highest energy efficiency Cortex-M0 : Lowest cost, low power Performance efficiency Cortex-M33 : Flexibility, control and DSP with TrustZone Cortex-M4 : Mainstream control and DSP Cortex-M3 : Performance efficiency Highest performance Cortex-M7 : Maximum performance, control and DSP Ref: https://www.arm.com/products/processors/cortex-m

Cortex-M Performance Comparison

CoreMark of Cortex-M cores

Dhrystone 2.1 Comparison Chart

Cortex-M0/M4 Power Consumption

Cortex-M0 Feature NVIC ARMv6-M Thumb instruction set Thumb-2 Technology Optionally, an ARMv6-M compliant 24-bit SysTick timer A 32-bit hardware multiplier The system interface supports either little-endian or byte invariant big-endian data accesses. The ability to have deterministic, fixed-latency, interrupt handling. Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling C Application Binary Interfae compliant exception model (C-ABI) Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature. NVIC 1,2,4,8,16,24, or 32 external interrupt inputs, each with four levels of priority Dedicated Non-Maskable Interrupt (NMI) input Support for both level-sensitive and pulse-sensitive interrupt lines Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support

Cortex-M0 Feature Optional debug support Zero to four hardware breakpoints Zero to two watchpoints Program Counter Sampling Register (PCSR) for non-intrusive code profiling Single step and vector catch capabilities Support for unlimited software breakpoints using BKPT instruciont Non-intrusive access to core peripherals and zero-waitstates system slaves through a compact bus matrix Full access to core registers when the processor is halted Optional, low gate-count CoreSight compliant debug access through a Debug Access Port (DAP) supporting either Serial Wire or JTAG debug connections. Bus interfaces Single 32-bit AMBA-3 AHB-Lite system interface that simple integration to all system peripheral s and memory Single 32-bit slave port that support the DAP

Cortex-M0 Functional Block Diagram

ARM 3-stage pipeline architecture register bank, which stores the processor state. barrel shifter, which can shift or rotate one operand ALU, which performs the arithmetic and logic functions  address register and incrementer, which select and hold all memory addresses and generate sequential addresses when required. data register, which hold data passing to and from memory. instruction decoder and associated control logic 3-stage pipeline

AHB bus interconnection

AHB bus transfer

APB bus transfer APB Write APB Read

Processor Core Registers

Porgram Status Register Application Program Status Register Interrupt Program Status Register Execution Program Status Register

IPSR bit assignments

Memory Access Behavior

Memory region shareability and cache policies

Memory region shareability and cache policies

Byte-invariant big-endian format

Little-endian format

Properties of the different exception types

Cortex-M0 Instruction Sets

Cortex-M Instruction Sets

Cortex-M Instruction Sets

CMSIS-CORE CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines: Hardware Abstraction Layer (HAL) : defines SysTick, NVIC, System Control Block registers, FPU registers, and core access fuctions Methods to organize header files : naming convention for device specific interrupts Methods for system initialization : SystemInit() Intrinsic functions : used to generate CPU instructions that are not supported by standard C functions A variable to determine the system clock frequency which simplified the setup of SysTick timer CMSIS-CORE User Files

References http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf