Straw readout status Run 2016 Cover FW SRB FW

Run experience Since the start of 2016 campaign straw detector works reliably and without major problems T0 shift easily detectable and adjusted October FW with T0 fix November New FW tested successfully with 100% intensity beam

New Firmware Overall speed increase Definition – Mega Measurement “MM” Cover Improved TDC speed, 1 measurement in 6.25ns -> 0 dead time Output speed 2x New link design to fix T0 problem SRB Input FPGA reorganized New cover links (as cover FW) Event manager FPGA Input reorganized trigger matching 2x speed Second Ethernet interface Fast SRB links now 2.5Gbs (1.25Gb/s old FW) Used more efficiently Definition – Mega Measurement “MM” Millions of measurements processed Independent from number of bits

New Firmware Old FW New FW Cover FPGA 10 MM 20 MM Fe_intf FPGA (input group) 40 MM 80 MM in, 60 MM out Event_mgr FPGA (SRB total) 80 MM 240 MM in, 160 MM TM Data rates from 2015 data (Mega measurements) Straw detector after upgrade will be able to handle 2 times nominal beam intensity continuously Factor bigger then 2 will be handled for few milliseconds nominal 2 x nominal 3 x nominal 4 x nominal ‘hot’ straws cover (only few out of ~500) 10 MM 20 MM 30 MM (limit 20) 40 MM (limit 20) Average cover 3 MM 6 MM 9 MM 12 MM 4 covers to SRB (input group) average 24 MM 36 MM 48 MM SRB total (event mgr) 96 MM 144 MM 192 MM (limit 160)

New Firmware Bug fixes New features T0 Lost packets in PC farm EOB bit in the last packet New features Various places New link start procedure with phase measurement Monitoring data quality Lost data

Cover firmware – TDC TDC speed improved, still 225ps resolution

Cover data flow Few stages of data buffering and flow organization One measurement in 6.25ns Few stages of data buffering and flow organization FIFO 512 TDC R 2x LINK 10MM (320 Mb/s) TDC F FIFO 512 FIFO 512 FIFO 2048 160MM each FIFO 512 FIFO 2048 16 straws FIFO 512 FIFO 512 Note: One measurement 24 bits, needs 3 write accesses to link One ‘comma’ character for data quality check Every TDC counts total number of hits and lost hits

SRB – FE_INTF FPGA Input 80MM Improved in new FW version LINK 60MM Cover link 20MM (2 x 320Mb/s) FIFO 8192 Cover link 20MM (2 x 320Mb/s) LINK 60MM (2Gb/s) FIFO 8192 SYNCH FIFO 8 Cover link 20MM (2 x 320Mb/s) FIFO 8192 Cover link 20MM (2 x 320Mb/s) Few stages of data buffering and flow organization Data quality checks and counters of lost data FIFO 8192

SRB – EVENT_MGR Improved in new FW version 2x 1Gb ETH 4x 60MM FIFO 1024 FE_INTF link 2Gb/s 2x 1Gb ETH FIFO 1024 FE_INTF link 2Gb/s SYNCH FIFO 2048 TRIGGER MATCH 160MM FIFO 1024 FE_INTF link 2Gb/s FIFO 1024 FE_INTF link 2Gb/s

Buffer with few levels and priorities Dataflow summary COVER FE_INTF EVENT_MGR Buffer with few levels and priorities 20MM TDC 225ps, ‘0’ dead time 60MM Trigger matching 160MM Online monitor 20MM 20MM 1G ETH 20MM 1G ETH 60MM 60MM 60MM

Straw data flow summary All parts of straw readout designed to more then expected rate Safety factors 2 -> 4 continuous in comparison with 100% beam intensity data flow More then 2 for few milliseconds All data receiving and reformatting parts will be monitored for possible data loss All covers and SRBs checked with VME online monitoring after EOB Any data loss is reported but in normal operation should be avoided