UNIT II : BASIC ELECTRICAL PROPERTIES MOS Transistor UNIT II : BASIC ELECTRICAL PROPERTIES Sreenivasa Rao CH Department of Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad-500090 Email: sreenivasarao_ch@vnrvjiet.in Web: http://www.vnrvjiet.ac.in/vlsidesign/ VLSI Design 06/01/2009

Out Line MOS Transistor operation Threshold Voltage

Overview of MOS Metal-oxide semiconductor (MOS) integrated circuits (ICs) have become the dominant technology in the semiconductor industry With MOS, it is possible to have a lot of millions of transistor on a single chip It allows the fabrication of a complete 64-bit microprocessor or some Gbyte memory The main reason is that MOS ICs exceed the bipolar transistors: in functional density (the number of functions performed on a single chip), MOS transistors are simpler to fabricate

What is a MOS Transistor? MOS transistor consists of semiconductor material (silicon) on which is grown a thin layer (1...50 nm) of insulating oxide, topped by a gate electrode The gate electrode was originally metal, specifically aluminium, but is now more commonly a layer of polycrystalline silicon (referred to as polysilicon) Source and drain pn-junctions are formed with a small overlap with the gate

Metal-Oxide-Semiconductor Transistors Most modern digital devices use MOS transistors, which have two advantages over other types greater density simpler geometry, hence easier to make MOS transistors switch on/off more slowly MOS transistors consist of source and drain diffusions, with a gate that controls whether the transistor is on Gate S D metal n+ n+ silicon dioxide p monosilicon 204424 Digital Design Automation October 19, 2017

Review - Transistor Structure

The MOS Device (3D structure) Contacts Poly on thin Gate oxide Metal 1 N+ Implant .18µm technology (hcmos8)

N Transistor Operation - Cutoff Vgs << Vt : Transistor OFF Majority carrier in channel (holes) No current from source to drain

N Transistor Operation - Subthreshold 0 < Vgs < Vt : Depletion region Electric field repels majority carriers (holes) Depletion region forms - no carriers in channel No current flows (except for leakage current)

N Transistor Operation - ON Vgs > Vt , VDS=0: Transistor ON Electric field attracts minority carriers (electrons) Inversion region forms in channel Depletion region insulates channel from substrate Current can now flow from drain to source!

N Transistor Operation - Linear Vgs > Vt , VDS <VGS -VT : Linear (Active) mode Combined electric fields shift channel and depletion region Current flow dependent on VGS, VDS

Linear Region With a small positive bias on the gate, electrons can enter the channel and a current flow from source to drain is established In the low drain bias regime, the drain current increases almost linearly with drain bias The channel resistance is determined by the electron concentration in the channel, which is a function of the gate bias Therefore, the channel acts like a voltage controlled resistor whose resistance is determined by the applied gate bias As the gate bias is increased, the slope of the I-V characteristic gradually increases due to the increasing conductivity of the channel We obtain different slopes for different gate biases This region where the channel behaves like a resistor is referred to as the linear region of operation The drain current in the linear regime is given by

N Transistor Operation - Saturation Vgs > Vt , VDS >VGS -VT : Saturated mode Channel “pinched off” Current still flows due to electron drift Current flow dependent on VGS

Saturation Region For larger drain biases, the drain current saturates and becomes independent of the drain bias Naturally, this region is referred to as the saturation region To obtain the drain current in saturation, this VD,sat value can be substituted in the linear region expression, which gives

P Transistor Operation Opposite of N-Transistor Vgs >> Vt : Transistor OFF Majority carrier in channel (electrons) No current from source to drain 0 > Vgs > Vt : Depletion region Electric field repels majority carriers (electrons) Depletion region forms - no carriers in channel No current flows (except for leakage current) Vgs < Vt , VDS=0: Transistor ON Electric field attracts minority carriers (holes) Inversion region forms in channel Depletion layer insulates channel from substrate Current can now flow from source to drain!

P Transistor Modes of Operation Vgs <Vt , VDS >VGS -VT : Linear (Active) mode Combined electric fields shift channel and depletion region Current flow dependent on VGS, VDS Vgs < Vt , VDS <VGS -VT : Saturation mode Channel “pinched off” Current still flows due to hole drift Current flow dependent on VGS

N-type Transistor structure

I-V Characteristics of MOS Transistors linear saturation n transistor linear saturation p transistor

Ideal Transistor Equations Cutoff Region: Vgs < Vt Linear Region Vds < Vgs - Vt Saturated Region Vds ≥ Vgs - Vt

More about Transistor Equations More about k' µ - effective surface mobility of carrier e - permittivity of gate insulator tox - thickness of gate insulator Beta - a measure of gain Important things to remember: these equations are approximations Use circuit simulator (e.g. PSpice) for more accurate modeling k' = me t ox b = ¢ k W L

Comparison of Enhancement and Depletion Mode MOSFETs Gate Source Drain p-type silicon substrate n+ p+ n-type silicon substrate 21

0.5 m transconductances From a MOSIS process: n-type: p-type: kn’ = 73 A/V2 Vtn = 0.7 V p-type: kp’ = 21 A/V2 Vtp = -0.8 V

Current through a transistor Use 0.5 m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. Vgs = 2V: Id = 0.5k’(W/L)(Vgs-Vt)2= 93 A Vgs = 5V: Id = 1 mA

MOSFET gate as capacitor Basic structure of gate is parallel-plate capacitor: gate + SiO2 tox Vg - substrate

Parallel plate capacitance Formula for parallel plate capacitance: Cox = ox / tox Permittivity of silicon: ox = 3.46 x 10-13 F/cm2 Gate capacitance helps determine charge in channel which forms inversion region.

Threshold voltage Components of threshold voltage Vt: Vfb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surface charge. s = surface potential (about 2f). Voltage on paralell plate capacitor. Additional ion implantation.

Body effect Reorganize threshold voltage equation: Vt = Vt0 + Vt Threshold voltage is a function of source/substrate voltage Vsb. Body effect  is the coefficienct for the Vsb dependence factor.

Example: threshold voltage of a transistor Vt0 = Vfb + s + Qb/Cox + VII = -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0.92 V = 0.68 V Body effect n = sqrt(2qSiNA/Cox) = 0.1 DVt = n[sqrt(s + Vsb) - sqrt(s)] = 0.16 V

Gate voltage and the channel source current drain Vds < Vgs - Vt Id gate source current drain Vds = Vgs - Vt Id gate source drain Vds > Vgs - Vt Id

Types of leakage current. Weak inversion current (a.k.a. subthreshold current). Reverse-biased pn junctions. Drain-induced barrier lowering. Gate-induced drain leakage; Punchthrough currents. Gate oxide tunneling. Hot carriers.

Threshold Voltage Depends on gate capacitance, physical constants When Vsb=0: Permittivity of SiO2 = 3.9e0 Oxide thickness (cm) Flatband voltage Work function difference Surface potential Adjustment - Ion Implant Charge stored in depletion region

Threshold Voltage - Body Effect Vt increases when Vsb >0

Wires and Vias Creating wires (review): Deposit insulator on chip (SiO2) Deposit conducting material on chip Selectively remove using photolithography Use multiple layers so wires can cross over each other Vias (Contacts) - Connect between layers “cuts” etched through insulator Metal connects between layers (with significant resistance) Wafer

Wires and vias metal 3 metal 2 vias metal 1 poly poly p-tub n+ n+

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