EMC Models

Summary Models, what for ? IC Models for EMC Core Model Package model Test-bench models Emission measurements/simulations Immunity measurements/simulations Conclusion The presentation is laid out as follows: why EMC models, the definition of a macro-model for an integrated circuit, the package models, the correlation with measurements and the future of EMC models. October 17

Models – What for ? IC DESIGNERS WANT TO PREDICT EMC BEFORE FABRICATION Noise margin Switching Noise on Vdd IC designers want to predict power integrity and EMI during design cycle to avoid redesign EMC models and prediction tools have to be integrated to their design flows Short time-to-market Cost of redesign: several million € IC designers want to predict voltage drops inside their chips, which has to remain lower than noise margins. Moreover, as their components are submitted to EMC constraints depending on the application domain, they want also to forecast parasitic emission and vulnerability of their circuits to EMI. Therefore, they have to deal with PI and EMI problems during conception cycles, so that they have to integrate EMC models and prediction tools to their design flow. On top of it, IC designers have to be EMC concerned ! October 17

Models – What for ? EQUIPMENT DESIGNERS WANT TO PREDICT EMC BEFORE FABRICATION © Siemens Automotive Toulouse Most of the time, EMC measurements are performed once the equipment is built. No improvements can be done at conception phase. Predict EMC performances  IC, board, equipment optimizations However, need of non-confidential IC models (black box models) Equipment designers want to predict the parasitic emission of their equipment, such as the automotive engine control system shown here, by courtesy of Siemens Automotive SA. The short distance scan of the equipment shows specific areas with strong emission (In red), and other areas with low emission (in blue). Most of the time, the emission measurement is performed once the equipment is fabricated, and software tools do not predict accurately the measured emission. Predict EMC performances allows an optimization of design of PCB and systems before fabrication. However, models of ICs used in applications are required. That’s why equipment designers ask IC manufacturers for IC models. IC manufacturers have to provide models which predicts correctly emission and immunity performances of their ICs without giving any confidential information about their technology and design techniques. October 17

Models – What for ? EMC VALIDATED BEFORE FABRICATION Models DESIGN Design Guidelines Models Training DESIGN Architectural Design Design Entry Design Architect EMC Simulations Compliance ? FABRICATION Including reduction techniques in the early design phases and simulating the parasitic emission before fabrication, as suggested by low emission design methodologies, requires efficient IC models and adequate tools. Models related to EMC start to appear, as well as specific tools to handle the EMC behaviour of the IC. NO GO EMC compliant GO October 17

IC models for EMC EMC MODELS DEPENDS ON THE TARGETED COMPLEXITY, THE LEVEL OF CONFIDENTIALITY OF INFORMATION. Level 100 V(f), 100 Z(f) Equipment V, Z LEECS ICEM Dipoles 102 R,L,C,I 101 R,L,C,I 101 dipoles Board Component Expo PowerSI 104 R,L,C,I Physical 106 R,L,C,I spice Complexity low medium high x-high Confidentiality October 17

Simulated Emission spectrum IC models for EMC GENERAL FLOW TO BUILD AN EMC MODEL AND PREDICT EMC PERFORMANCES IEC 62433 Test bench Model Test board Model Package Model Core – I/O Model EMC Model for the circuit Simulated Emission spectrum Electrical Simulation The general flow to build a model of IC and simulate EMC performances (emission or susceptibility). Concerning simulation, our task is to define a model of the board including the IC, the package, the measurement probe and the test board. Each part requires some specific model, extracted from layout, design information, technical documentation, or measurement. Typically, simulations are performed with electrical simulator (SPICE, VHDL-AMS). October 17

IC models for EMC THE IEC 62433 PROJECT IEC 62433-2 ICEM-CE Conducted RF emission IEC 62433-3 ICEM-RE Radiated RF emission IEC 62433-4 ICIM-CI Conducted RF immunity IEC 62433-5 ICIM-RI Radiated RF immunity October 17

IC models for EMC THE IEC 62433 PROJECT Conducted mode Radiated mode Emission ICEM-CE ICEM-RE IEC 62433 - 2 IEC 62433-3 Immunity ICIM-CI ICIM-RI IEC 62433-4 IEC 62433-5 Impulse immunity IEC 62433-6 Intra-bloc EMC Intra - bloc IEC 62433-7 Standard available Research undergoing Draft of standard October 17

IC models for EMC IA IEC 62433-2 – “ICEM Conducted Mode” PDN Package IT IA PDN Package October 17

Extraction of internal current waveform Core model INTERNAL ACTIVITY (IA) - CURRENT SOURCE EXTRACTION 16 bit processor 16 MHz 32 bit processor 500 MHz Extraction of internal current waveform I I 3 A Modeling the core activity corresponds to the extraction of the noise current, by one or several equivalent current sources. Waveforms are often complex and a 1st order approximation is to model them with triangular waveforms. 100 mA 62.5 ns time time 2 ns 1st order assumption : model core activity by triangular waveform current source October 17

Core model In this course INTERNAL ACTIVITY (IA) – FROM PHYSICAL TO FIRST-ORDER ESTIMATION In this course Physical Transistor level (Spice) Huge simulation Limited to analog blocks Interpolated Transistor level Difficult adaptation to usual tools Limited to 1 M devices Simple, not limited Fast & accurate Gate level Activity (Verilog) Activity estimation from data sheet Very simple, not limited Immediate, not accurate time (ns) 200 400 600 800 1000 1200 20 40 60 80 100 120 140 Activity Equivalent Current generator Extraction The modeling of the core can be performed at various levels. We illustrate here four approaches. The first one, acting at physical level, consists in the analog simulation of the core. This approach is limited to small blocks, typically 100 to 1000 transistors. The current consumed on the VDD and VSS supply lines are accurately predicted. For large blocks, a working approach consists in the use of pseudo analog simulation, where the physical set of equations is replaced by an approximated tabulated array of data. This approach speeds up considerably the simulation, which remains at analog level, and gives the current flow on VDD and VSS almost as accurately as for the pure analog simulation. However, the supply voltages are considered perfect. For several millions of devices, the only remaining approach is based on the gate current approximation, using a statistical approach for elementary gate current. The total current is the sum of elementary currents, each one being characterized individually under typical loading and switching conditions. Finally, the last approach is the less accurate but the fastest method to provide a rough approximation of the internal activity. This method is based on the estimation of the activity from several basic data like the number of gates, the average activity %, the technology, clock frequency. October 17

Equivalent passive model Substrate, interconnections metallization Core model PASSIVE DISTRIBUTION NETWORK (PDN) Complex network of interconnections, vias and on-chip capacitances Coupling path for noise through the IC Require extraction of impedance between Vdd and Vss. Possible modeling by an equivalent passive model Equivalent passive model The IC is composed of a complex network of interconnections, via, on-chip capacitances. It creates a complex impedance structure between Vdd and Vss, which influes on the propagation of the noise inside and outside the chip. The impedance between Vdd and Vss is mainly capacitive and resistive. For large chip, an inductive contribution can be taken into account. Substrate, interconnections metallization Capacitive behavior October 17

Emission measurement/simulation PDN DESCRIPTION IN A STANDARD FORMAT Several ways to describe schematic diagrams SPICE is the most usual UTE (France) works on an XML description of circuits in a more general way, including SPICE October 17

H. Quaresma, PhD 2007, IST Lisboa, Portugal Core model INTERNAL BLOCK COUPLING (IBC) H. Quaresma, PhD 2007, IST Lisboa, Portugal October 17

Core model INTERNAL BLOCK COUPLING (IBC) ATMEL 90 Case study Logic-to-analog path: R (1-10 ohm), C for HF October 17

Core model INTERNAL BLOCK COUPLING (IBC) DSPIC 33F Case study Data sheet information October 17

Core model IA ICEM IN IC-EMC - DOUBLE LC SYSTEM PDN Rvdd Lvdd ICEM-CE model (IEC 62433-2) Package model IC model Rvdd Lvdd External VDD IA LPackVdd PDN Cd Cb LPackVss IA External VSS Rvss Lvss Primary resonance Secondary resonance Frequency Emission level From the double resonance observation, ICEM model has been proposed. This model is based on a double LC system. It is composed of the IC model and the package model. These 2 LC make appear two resonances on the emission spectrum. Low L,C values => High resonant frequency October 17

Core model IC-EMC EXPERT TOOL An ICEM-based emission model from IC specification in one single click October 17

Input driver I(V) characteristics Output driver I(V) characteristics Core Model ADDING IOS - IBIS: INPUT BUFFER I/O SPECIFICATION Input driver I(V) characteristics [IBIS Ver] 2.1 [Date] March 17,2011 [File Name] dsPIC33FJ128GP706.ibs [File rev] 1.0 [Component] dsPIC33FJ128GP706 [manufacturer] MICROCHIP [Package] | R_pkg 19.05m 21.2m 16.9m L_pkg 3.025nH 2.61nH 3.44nH C_pkg 0.269pF 0.268pF 0.270pF … IBIS file Output driver I(V) characteristics Here is an example of IBIS description file, which gives some I(V) characteristics for I/Os. These data are helpful to produce equivalent models for I/Os. I/O modeling is very important for the prediction of I/O emission (model of I/O coupled with supply network model allows predicting the SSN), but also for I/O immunity prediction. I/O switching noise prediction I/O immunity prediction Very important for : October 17

Core Model IC PIN DECLARATION - MODELS October 17

Core Model MODEL DETAILS October 17

Core Model ADDING IOS – TUNE IO SWITCHING October 17

Core Model ADDING MANY IOS Equivalent EMC, but reduced complexity Merge buffers Merge loads Merge lines October 17

Electromagnetic solver Package Model S PDN – ADVANCED MODEL USING 3D ELECTROMAGNETIC SOLVER Electromagnetic solver S parameter black box Method of moment FEM FDTD PEEC… Geometrical meshed model Simulation of EM behavior of packages Extraction of package model Electrical models compatible with electrical simulator (SPICE-like) Modeling the package is mandatory for EMC of IC analysis since it induces switching noise due to internal activity of the component and generates resonances at high frequency. Different techniques exist to extrat an equivalent model. The first one is based on the use of a 3D electromagnetic solver (MoM, FEM, FD-TD,PEEC). A meshed geometrical model is required for the simulation. The electromagnetic method depends on the expected format for results : time or frequency domain, S parameter box, transmission line or RLCG lumped models. Methods which provides RLCG matrix, like PEEC, are well adapted for electrical simulation flows. RLC matrix October 17

Package Model PDN – ADVANCED MODEL FROM S PARAMETERS EXTRACTION Coplanar probe Package Vector Network Analyzer Extraction of package model from measurement Calibration plane issues from hundreds of MHz Require good knowledge in RF measurement A vector network analyzer is well adapted to extract an electrical or RLC lumped model for packages. It gives a frequency description of the electrical behaviour of the package. Another way to extract package model is TDR. The main issue of VNA measurement is linked with the calibration plane of the equipment. It measures S parameters or input impedance of every devices placed after this plane. If the package is mounted on a board, the contributions of board and package are measured and it is difficult to remove board influence from the measurement. The best method to extract only the influence of package is the use of coplanar miniature probe. October 17

Package Model CASE STUDY – DSPIC 33F On-chip decap Package inductance z11-dspic-vdd_10-vss_9.z October 17

Time Domain Simulation Emission measurement/simulation CONDUCTED/RADIATED EMISSION PREDICTION Simulations Measurements Core Model Elec. package Board DUT IC Model 1 To receiver Spectrum analyzer Time Domain Simulation FFT of Vanalyzer(t) Compare spectrums EMC model Measurements Here is a concrete example of simulation compared with measurements, using the conducted 1ohm probe. This is the same process for TEM/GTEM radiated emission measurement. The measurement is provided by a high quality frequency analyzer, and the model is given by a SPICE analog simulation in time domain, converted in the appropriate units (dBµV vs frequency) by fast Fourier transform. October 17

Emission measurement/simulation ICEM-CE CASE STUDY – DSPIC 33F Core only October 17

Emission measurement/simulation ICEM-CE CASE STUDY – DSPIC 33F Core + 16 ADDR 20dB more noise than core October 17

Magnetic near field scan of a 16 bit microcontroller Emission measurement/simulation ICEM-RE – CURRENT DIPOLE THEORY H1 H2 P Magnetic near field scan of a 16 bit microcontroller Vss I(vss) chip I(vdd) Vdd Package is the main contributor of the radiated emission of an IC Magnetic field emission is generated by the flowing of parasitic current through package pins October 17

Emission measurement/simulation ICEM-RE – SIMULATION/MEASUREMENT Scan Simulations Scan Measurements Spectrum analyser H[x,y] at given f, given z Positionning [x,y] Geometrical package model Core Model Elec. package Analog Time Domain Simulation Fourier Transform of I(t) H[x,y,z] of I(f) Compare scans October 17

Emission measurement/simulation ICEM-RE – RADIATING DIPOLES PDN IT IA IT October 17

IC models for EMC IEC 62433-4 – “ICIM CONDUCED IMMUNITY” The package and die impedance act as a coupling path for RF interference (Vin, Iin) to the active blocks, Filtering effect and/or distortion through the PDN and produce (Vr,Ir). The IB block describes how the circuit reacts to internal perturbations, and can be represented as (Vout,Iout) for monitoring the failure October 17

Monitoring of the failure IC models for EMC IEC 62433-4 – “ICIM CONDUCED IMMUNITY” IB ICIM – immunity model Package RF disturbance Coupling path Package PDN Monitoring of the failure IC PDN Internal Behaviour IB External pins detection Silicon die PDN = Passive Distribution Network PDN Package Close to ICEM Add Diodes (camp, back-to-back, ESD, EOS) Close to ICEM-CE New! October 17

Susceptibility criterion IC models for EMC IEC 62433-4 – “ICIM CONDUCED IMMUNITY” Coupling path model RF generator model Injection model Functionnal model Susceptibility criterion + Perturbation source + Injection device model + DUT power supply + Internal Behavior (IB) Power limit Voltage threshold Overcurrent SNR degradation LSB degradation…. + Extraction of power injection + PCB model + DUT input structure model + Behaviour of sensitive & non-linear parts + Passive Decoupling Network (PDN) October 17

Susceptibility measurement/simulation From ICEM SUSCEPTIBILITY PREDICTION MODEL From IBIS Time Amplitude Disturbance model Coupling path model IC model Supply network Z(f) I/O Functional model output input clock Vdd Vss Resonance Finally, could the ICEM model be used in susceptibility? This is still an opened question but the UTE task force in France has started a debate and technical research on this topic. The goal is to propose some enhancements in the structural description of IC models in order to predict the first order response of the IC to external electromagnetic wave. The figure gives a global view of a susceptibility model which is composed of the disturbance model (injection device) and the IC model. Some parts of ICEM model, as the supply network are reused. IBIS can provide valuable information about I/O behavior. ICIM – CE immunity model Reuse of standard non-confidential models (ICEM, IBIS) Susceptibility peaks linked with supply network anti-resonances October 17

Susceptibility measurement/simulation SUSCEPTIBILITY SIMULATION FLOW Aggressed IC Model (ICEM) Package and IO model (IBIS) RFI and coupling path model (Z(f)) Set RFI frequency IC-EMC Susceptibility threshold simulation Increase RFI frequency Increase V aggressor Time domain simulation WinSPICE Criterion analysis Extract forward power IC-EMC October 17

Test bench model TEM Cell Near-field scan DPI injection Electrical model extracted by S parameter measurements and electromagnetic simulations Test bench models should be generic Limited frequency range due to influence of parasitic elements, apparition of high order propagation mode TEM Cell DPI capacitance Near-field scan DPI injection October 17

Susceptibility case study DPI ON A 330 OHM LOAD Immunity > Dpi330ohm October 17

Roadmap IEC 62433 – PRESENT, FUTURE Bandwidth Type 2005 2010 2015 2020 < 3 GHz Emission model Conducted Emission 62433-2 Sol. Exist PDN, IA Ind. use ICEM-CE Radiated Emission 62433-3 Sol. exist Sol. Exist – Radiated dipole ICEM-RE Bandwidth Type 2005 2010 2015 2020 < 3 GHz Immunity model Conducted Immunity 62433-4 Sol. exist Draft ICIM-CI Ind. Use Radiated Immunity 62433-5 Sol. Exist – Radiated dipole ICIM-RI October 17

Integrated Circuit (ICEM, ICIM) Generalization - upscale Equipment ) Printed Circuit Board Equipment Integrated Circuit (ICEM, ICIM) PDN Equipment Passive PDN Distribution I A Network Internal activity Printed Circuit Board PDN IB Board IEC 62433 Immunity Integrated Circuit (ICEM, ICIM) S,P behavioral Other integrated circuit Other printed circuit board October 17

Generalization - downscale Integrated Circuit (ICEM, ICIM) Sub-component Silicon die October 17 October 17

Conclusion EMC models can help earn/save money Macro-models of ICs include core, I/O and package modeling The core model is based on current evaluation and on-chip capacitance The package model is based on RLC Good prediction of emission and susceptibility up to 2 GHz Soon, requirements up to 3-10 GHz This presentation is now completed. We detailed how an IC design methodology including EMC modeling and prediction may help saving money. We described the structure of the IC macro-model that enabled and accurate prediction of conducted/radiated emission, through a reduced set of simple elements. Then, we explained how the model can be feed with physical data at printed circuit, package, I/O and core level. We showed interesting correlation between measurements and simulation for a conducted 1ohm and TEM cell approaches, up to 1GHz. The future of EMC models, for bandwidth up to 18GHz and susceptibility have also briefly been discussed. October 17