Computer System Structures Interrupts Interrupts types and classification Interrupt driven OS Interrupt handling Generic routine, interrupt vectors, interrupt chaining Interrupt implementation in the system Interrupt controller priorities, masks, reentrancy Silberschatz, Operating System Concepts, 9th edition Chapter - 13.2.2.

Terminology Trap - Any kind of a control transfer to the OS Interrupt – The mechanism of control transfer.   System call: Synchronous (planned), program-to-kernel transfer SYSCALL instruction in MIPS INT - on x86 Exception: Asynchronous, program-to-kernel transfer exceptional events: div by zero, page fault, page protection err, executing an illegal opcode … Hardware Interrupt: Aysnchronous, device-initiated transfer network packet arrived keyboard event timer ticks mouse click information transfer finished (HDD, printer). Software interrupts (directly called by program instruction) CPU Internal hardware interrupts Caused by Software (the unexpected result of program instruction) Hardware interrupts (caused by devices)

What is the interrupt When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a fixed location. The fixed location usually contains the starting address where the service routine for the interrupt is located. The interrupt service routine executes; on completion, the CPU resumes the interrupted computation. An interrupt service (handler) routine is a procedure written specifically to handle a system calls, exceptions, or interrupts. Although different phenomenon cause system calls, exceptions, and interrupts, the structure of an interrupt service routine, or ISR (IHR), is approximately the same for each of these. ISR fixed location

System Calls A programmer initiated and expected transfer of control to a special handler routine ( particularly input/output) In many respects, a system call is nothing more than a specialized subroutine call. System Calls can be directly activated by the assembler invoking the number of the desired interruption with the INT or SYSCALL or other system instructions. Using system calls our programs become shorter Easy to understand Better performance due to short size

OS or BIOS System Calls OS system calls easier to use but they are slower since they are implemented using OS libraries BIOS system calls BIOS system calls are much faster Since they are part of the hardware, they are very basic and specific. Programs are not portable.

Exceptions Internal hardware interrupts as a result of user program instructions An exception is an automatically generated system call (coerced rather than requested) that occurs in response to some exceptional condition. Generally, there isn’t a specific instruction associated with an exception, instead, an exception occurs in response to some degenerate behavior of normal program execution. The difference System call syscall Exception add $1, $2, $3

External Hardware Interrupts Hardware interrupts, the third category that we will refer to simply as interrupts, are program control interruption based on an external hardware event (external to the CPU). These interrupts generally have nothing at all to do with the instructions currently executing; instead, some event, such as pressing a key on the keyboard or a time out on a timer chip, informs the CPU that a device needs some attention.

Interrupt driven Operating Systems Modern operating systems are interrupt driven. If there are no processes to execute, no I/O devices to service, and no users to whom to respond, an operating system will sit quietly, waiting for something to happen. After booting when the kernel is loaded the operating system starts executing the first process, such as "init," and waits for some event to occur. The occurrence of an event is usually signaled by an interrupt from either the hardware or the software.

Hardware Interrupt Mechanism Hardware may trigger an interrupt at any time by sending a signal to the CPU, usually by way of the system bus. Kernel Interrupt ID (N) Kernel routine1 Event (N) Signal (N) Kernel routine N Hardware Software Separate segments of codes are needed for different interrupt services. Different types of devices generate different types of interrupt signals corresponding to the different events happened on the devices. This signal and then the interrupt is accompanied with the interrupt identifier that identifies the event and the desired kernel service. When the interrupt occurs, the interrupt hardware saves the state of the user code switches to supervisor mode and dispatches to the kernel routine that implements the requested service.

System Call Mechanism Separate segments of codes are needed for different interrupt service. Usually, a program issues system calls by special instructions called a Software Interrupt. This instruction has an operand that identifies the desired kernel service. When a process executes the trap instruction, the interrupt hardware saves the state of the user code switches to supervisor mode and dispatches to the kernel routine that implements the requested service. Kernel Interrupt ID (N) Kernel routine1 Application OS Library SYSCALL(N) Signal (N) Kernel routine N Software Hardware Software

Interrupt driven Operating Systems

Common mechanisms of interrupts in different OS Each computer design has its own interrupt mechanism, but several functions are common. The interrupt must transfer control to the corresponding interrupt service routine. The interrupt architecture must also save the address of the interrupted instruction and the state of the interrupted process. More recent architectures store this information in the system stack After the interrupt is serviced, the saved return address is loaded into the program counter, and the interrupted computation resumes as though the interrupt had not occurred.

Interrupt Handling The interrupt handles the transfer of control to the appropriate interrupt service routine by Generic Routine Table of pointers – interrupt vector of addresses The straightforward method for handling this transfer would be to invoke a generic routine to examine the interrupt information. In MIPS this routine is at 8000 0180 address. Instead could be used the array or interrupt vector of addresses indexed by a unique device number to provide the address of the interrupt service routine for the interrupting device. In x86 architecture those vectors start from the 0000 0000 address.

Generic Routine vs Vectors Array The software analyzes the types of interrupts. Disadvantage: For large amount of interrupts the process will be slow.   Advantage: There is no special hardware created for different types of interrupts. The Software is flexible for changes. The hardware analyzes the types of interrupts. Advantage: For large amount of interrupts the process is fast. Disadvantage: Complex hardware. Not flexible.

Interrupt Chaining The purpose of a vectored interrupt mechanism is to reduce the need for a single interrupt handler to search all possible sources of interrupts to determine which one needs service. In practice, however, computers have more devices (and, hence, interrupt handlers) than they have address elements in the interrupt vector. A common way to solve this problem is to use the technique of interrupt chaining, in which each element in the interrupt vector points to the head of a list of interrupt handlers. This structure is a compromise between the overhead of a huge interrupt table and the inefficiency of dispatching to a single interrupt handler.

Example X86

User’s interrupt routine installation

User’s interrupt routine running

Interrupt implementation in the system This basic interrupt mechanism enables the CPU to respond to an asynchronous event, as when a device controller becomes ready for service. In a modern operating system, however, we need more sophisticated interrupt handling features.   We need the ability to defer interrupt handling during critical processing. 2. We need an efficient way to dispatch to the proper interrupt handler for a device without first polling all the devices to see which one raised the interrupt. 3. We need multilevel interrupts, so that the operating system can distinguish between high- and low-priority interrupts and can respond with the appropriate degree of urgency. In modern computer hardware, these three features are provided by the CPU and by the interrupt-controller hardware.

Understanding the Interrupt priority

Non maskable Interrupts. Priority Levels. Most CPUs have two interrupt request lines. One is the nonmaskable interrupt (NMI) which is reserved for events such as unrecoverable memory errors, or power related signals. The second interrupt line is maskable. It can be turned off (disable interrupts) by the CPU before the execution of critical instruction sequences that must not be interrupted. The interrupt mechanism also implements a system of interrupt priority levels. This mechanism enables the CPU to defer the handling of low-priority interrupts without masking off all interrupts and makes it possible for a high-priority interrupt to preempt the execution of a low-priority interrupt.

Interrupt Controller Interrupts invoked with interrupt lines from devices Interrupt controller chooses interrupt request to honor Mask enables/disables interrupts Priority encoder picks highest enabled interrupt Software Interrupt Set/Cleared by Software Interrupt identity specified with ID line CPU can disable all interrupts with internal flag Non-maskable interrupt line (NMI) can’t be disabled

An example of Network Card Interrupt