Weekly Group Meeting Report

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Presentation transcript:

Weekly Group Meeting Report Renjie Chen Supervisor: Prof. Shadi A. Dayeh

Summary In the past week, I was finishing the samples of high-density neural probes, and starting to work on Ni-InGaAs diffusion study. My target was to: (1) prepare enough neural probe samples to send back to UCSD for Si etching (2) Modify the mask design for Ni-InGaAs Fin structures (3) Fabricate Ni-InGaAs Fin structures for temperature dependent diffusion study

Bonding Process for Neural Probes The breaking of Ni leads during P100 etching, is probably due to the completely consumption of Ni during bonding process. By modifying the metal stacking layers, we prevent the Ni to be totally reacted and preserve a thick layer of Ni for etching mask. Ti/Pd/Ti/Ni Ti/Pd/Ti/Ni/Ti/Ni

Mask Design Modification Previous Study: Fix RTA annealing temperature at 250 ‘C Fin width Dependent (50nm, 80nm, 100nm, 120nm, 150nm, 250nm, 550nm) Time Dependent (5min, 20min, 40min, 60min, 90min) Plan: Annealing Temperature 220’C 280’C Fin width design 20nm, 40nm, 60nm, 80nm, 100nm, 150nm, 200nm, 500nm Time Sequence 5min, 10min, 20min, 40min, 60min, 90min,120min 2min, 5min, 10min, 20min, 40min, 60min, 90min

4um Gap 6um Gap 8um Gap

SEM images that characterizes the nickelide reaction in In0. 53Ga0 SEM images that characterizes the nickelide reaction in In0.53Ga0.47As FinFETs. (a) and (b) demonstrate the variations of nickelide propagation length with different channel orientations and width and otherwise same annealing conditions (T = 250 °C, t = 60 min). (c) and (d) demonstrate a clear nickelide-InGaAs interface with a fixed crystallographic relationship except for the largest Fin width which developed multiple of such interfaces. A vertical volume expansion can be inferred from angle-view SEM image in (d).

Ni-InGaAs Fin Structure Fabrication When I first arrived at CINT 3 weeks ago, I tried to transfer InGaAs layer onto Si twice and they were not successful. In one time, the InGaAs layer was separated from the Si wafer during HCl etching. In the other time, the InGaAs layer was also etching in the concentrated HCl solution. Now the bonding problem was solved, and I realized that the InP layer should be lapped down to below 100um (tricky for lapping process) in order to shorten the time that the samples are later on immersed in the HCl solution. At the same time, 3:1 HCl in DI should be used for elective etching of InP, because concentrated HCl will also dissolve InGaAs layer. Now 12 samples on two large chips have been processed, and the 2nd EBL step for Ni lines deposition has finished. The Fin writing will be processed tonight.

Plan Continue to finish the fabrication of Ni-InGaAs fin structures on Si wafer. -- EBL writing for Fin layer, followed by InGaAs dry etching and surface smoothing -- RTA will be perform at two temperature and different time interval for these 12 samples -- AFM will be used to measure the surface profile of the reacted Ni-InGaAs -- Measure & plot the nickelide length with different fin width and reaction time Wait for feedback from P100 etching on neural probe samples, and modify the process accordingly.

Thank you Q&A