Digital Design: Sequential Logic Principles Credits: Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 A.B. Marcovitz, Intro. to Logic and Computer Design, McGraw Hill, 2008 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

Sequential Circuits A sequential circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. In other words, sequential circuits must be able to ”remember” (i.e., store) the past history of the inputs in order to produce the present output. The information about the previous inputs history is called the state of the system. A circuit that uses n binary state variables to store its past history can take up to 2n different states. Since n is always finite, sequential circuits are also called finite state machines (FSM).

How can we remember …? The key to build storage circuits is feedback !! 1 time t t+d t+2d 1 Cg A storage element from Physics Unfortunately caps are not ideal they lose charge !!! A storage element model from Calculus

In short, sequential circuits are … circuits consisting of ordinary gates and feedback loops X1 X2 • • • Xn Z1 Z2 • • • Zn switching network

The simplest sequential circuit Two inverters and a feedback loop form a “static” storage cell The cell will hold value as long as it has power applied How to get a new value into the storage cell? selectively break feedback path load new value into cell "0" "1" "stored value" bistable cell (= state) D latch "remember" "load" "data" "stored value"

Analog analysis of the bistable cell Vin1 Vout1 = Vin2 Vout2 Vin1 = Vout2

Latches and Flip-Flops The two most popular varieties of storage cells used to build sequential circuits are: latches and flip-flops. Latch: level sensitive storage element Flip-Flop: edge triggered storage element Common examples of latches: S-R latch, \S-\R latch, D latch (= gated D latch) Common examples of flip-flops: D-FF, D-FF with enable, Scan-FF, JK-FF, T-FF

S-R (Set-Reset) Latch X Y NOR 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 S-R latch: similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R S Q QN

S-R latch operation S R QN Q =1 0= 0= S R QN Q =0 1 0= =1 S R QN Q =0 0= 0= S R QN Q =0 1 0= =1 S R QN Q =0 =1 =1 S R QN Q =1 1 =1 =0

S-R latch operation (cont’d) (hold) (reset) (set) (forbidden) Race Both Q and QN are 0 at the same time

Improper S-R latch operation Theoretically the circuit starts to oscillate QN Reset Hold Set Reset Set Race R S Q QN

R-S latch analysis Break feedback path Q(t) R Q Q(t+) S(t) R(t) QN S 0 0 1 0 X 1 Q(t) R(t) S(t) S(t) R(t) Q(t) Q(t+) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set not allowed next state equation: Q(t+) = S(t) + R’(t) Q(t) Q+ = Q* = S + R’ Q a.k.a. characteristic equation

Theoretical R-S latch behavior Q QN SR=10 SR=00 SR=01 SR=00 SR=10 Q QN 0 1 Q QN 1 0 Q QN 0 0 Q QN 1 1 SR=01 SR=10 SR=01 SR=01 SR=10 SR=11 SR=11 SR=11 State diagram states: possible values transitions: changes based on inputs possible oscillation between states 00 and 11 SR=00 SR=00 SR=11

Observed R-S latch behavior Q QN Very difficult to observe R-S latch in the 1-1 state one of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 a so-called "race condition" or non-deterministic transition Q QN 0 1 Q QN 1 0 Q QN 0 0 SR=10 SR=01 SR=00 SR=11 SR=00

S-R Latch timing Recovery time (trec) = minimum delay between negating S and R for them to do not be considered simultaneous trec and tpw are related. Both are a measure of how longs does it take for the latch feedback loop to stabilize Violations of tpw and trec causes metastability.

S-R Latch SN(t) RN(t) Q(t) Q(t+) 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 0 X 0 0 1 X hold reset set not allowed RN SN Q(t) next state equation: Q(t+) = S’(t) + R(t) Q(t) X 1 0 0 1 0 Q(t) RN(t) SN(t) Q+ = Q* = S’ + R Q

D Latch (= Transparent Latch)

D-Latch Timing Parameters The D Latch eliminates the S=R=1 problem of the SR latch However, violations of setup and hold time still cause metastability

Clock signals Clocks are regular periodic signals used to specify state changes

D Flip-Flop (positive edge triggered) More compact Truth Table Functional Table Truth Table D Q+ 0 0 1 1 Notice: the little triangle ! Next state equation: CLK D Q inputs sampled on rising edge; outputs change after rising edge

Timing Behavior of a DFF (positive edge triggered)

Setup and hold times for an edge-triggered DFF

Minimum clock period T ? tpINV = 2 ns tpFF = 5 ns tsuFF = 3 ns T = 9 ns T = 15 ns Example with T = 15 ns Example with T = 9 ns

Minimum clock period T ? (cont’d) tpINV = 2 ns tpFF = 5 ns tsuFF = 3 ns Observation: thFF doesn’t affect this calculation Tmin = 10 ns

D Flip-Flop (negative edge triggered) inputs sampled on falling edge; outputs change after falling edge

DFF with asynchronous preset and clear

DFF with asynchronous preset and clear (cont’d)

DFF with enable Do not even think about it !!! D Reliable alternative CK 1 Q Q’ EN CLK Reliable alternative

DFF with enable (cont’d)

Scan DFF

Design for testability: scan chains

JK Flip Flop (rising edge triggered) = More Compact Truth Table Truth Table Functional Table J K Q+ 0 0 Q 0 1 0 1 0 1 1 1 Q’ Next state equation:

Toggle Flip Flop (rising edge triggered) More compact Truth Table Truth Table T CK Q Q’ CLK T Q+ 0 Q 1 Q’ CLK T Q

Activity Design a JK-FF and a T-FF using D-FFs Design a D-FF and a T-FF using JK-FFs Design a D-FF and a JK-FF using T-FFs

Summary of latches and flip flops

Comparison of latches and flip-flops D Q QFF D CLK QFF Qlatch CLK positive edge-triggered flip-flop D Q G Qlatch CLK transparent (level-sensitive) latch behavior is the same unless input changes while the clock is high

Comparison of latches and flip-flops (cont’d) Type When inputs are sampled When output is valid unclocked always propagation delay from input latch change level-sensitive clock high ( ∏ ) propagation delay from input latch (Tsu/Th around falling change or clock edge edge of clock) (whichever is later) master-slave clock high ( ∏ ) propagation delay from falling flip-flop (Tsu/Th around falling edge of clock edge of clock) positive clock L-to-H transition () propagation delay from rising edge-triggered (Tsu/Th around rising edge of clock flip-flop edge of clock)