SIGNAL TRAINING SCHOOL – BORDER SECIRITY FORCE - TIGRI

Slides:



Advertisements
Similar presentations
Sequential Logic Building Blocks – Flip-flops
Advertisements

1 Fundamentals of Computer Science Sequential Circuits.
Digital Logic Chapter 5 Presented by Prof Tim Johnson
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Sequential circuits The digital circuits considered thus far have been combinational, where the outputs are entirely dependent on the current inputs. Although.
Module 12.  In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the.
CSCE 211: Digital Logic Design. Chapter 6: Analysis of Sequential Systems.
1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits – I Flip-Flops A sequential circuit is a logic components whose outputs.
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Sequential Logic Flip-Flops and Related Devices Dr. Rebhi S. Baraka Logic Design (CSCI 2301) Department of Computer Science Faculty.
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
Sequential Circuit  It is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its.
Digital Logic Design CHAPTER 5 Sequential Logic. 2 Sequential Circuits Combinational circuits – The outputs are entirely dependent on the current inputs.
1 Sequential Circuit Latch & Flip-flop. 2 Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK.
Engineering Lecture 3 Digital Electronics by Jaroslaw Karcz.
COE 202: Digital Logic Design Sequential Circuits Part 1
Flip Flop
CENT-113 Digital Electronics 1 Flip Flops TI Type 502 Flip Flop: 1st production IC in 1960.
ECA1212 Introduction to Electrical & Electronics Engineering Chapter 9: Digital Electronics – Sequential Logic by Muhazam Mustapha, November 2011.
Sequential logic circuits
1 Lecture #11 EGR 277 – Digital Logic Ch. 5 - Synchronous Sequential Logic There are two primary classifications of logic circuits: 1.Combinational logic.
Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.
Sahar Mosleh PageCalifornia State University San Marcos 1 More on Flip Flop State Table and State Diagram.
Sequential Circuit Latch & Flip-flop. Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK flip-flop.
Chapter 6 – Digital Electronics – Part 1 1.D (Data) Flip Flops 2.RS (Set-Reset) Flip Flops 3.T Flip Flops 4.JK Flip Flops 5.JKMS Flip Flops Information.
Chapter5: Synchronous Sequential Logic – Part 1
 Flip-flops are digital logic circuits that can be in one of two states.  Flip-flops maintain their state indefinitely until an input pulse called a.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
7. Latches and Flip-Flops Digital Computer Logic.
Sequential Logic Circuit Design Eng.Maha Alqubali.
Sequential logic circuits First Class 1Dr. AMMAR ABDUL-HAMED KHADER.
Sequential Logic Design
FLIP FLOPS Binary unit capable of storing one bit – 0 or 1
Flip Flops.
LATCHED, FLIP-FLOPS,AND TIMERS
Homework Reading Machine Projects Labs Tokheim Chapter 9.1 – 9.6
Sequential Logic.
Lecture 8 Dr. Nermi Hamza.
Learning Outcome By the end of this chapter, students are expected to refresh their knowledge on sequential logic related to HDL.
Flip Flops.
FIGURE 5.1 Block diagram of sequential circuit
FLIP FLOPS.
Overview Introduction Logic Gates Flip Flops Registers Counters
Flip Flops.
Flip-Flop.
Sequential Circuits Most digital systems like digital watches, digital phones, digital computers, digital traffic light controllers and so on require.
CS1104 – Computer Organization
Sequential Logic Jess 2006.
Sequential Logic and Flip Flops
CISE204: Design of Digital Systems Lecture 18 : Sequential Circuits
Flip Flop.
Assistant Prof. Fareena Saqib Florida Institute of Technology
ECE Digital logic Lecture 16: Synchronous Sequential Logic
Digital Logic Design Sequential Circuits (Chapter 6)
Registers and Counters Register : A Group of Flip-Flops. N-Bit Register has N flip-flops. Each flip-flop stores 1-Bit Information. So N-Bit Register Stores.
LECTURE 15 – DIGITAL ELECTRONICS
Satish Pradhan Dnyanasadhana college, Thane
Sequential Logic and Flip Flops
Digital Logic Structures Logic gates & Boolean logic
Instructor: Alexander Stoytchev
Instructor: Alexander Stoytchev
Computer Architecture and Organization: L02: Logic design Review
FLIP-FLOPS.
Synchronous sequential
Synchronous Sequential
Flip-Flops.
Sequential Digital Circuits
Week 11 Flip flop & Latches.
Digital Electronics and Logic Design
Presentation transcript:

SIGNAL TRAINING SCHOOL – BORDER SECIRITY FORCE - TIGRI M.O.I Flip-flops An introduction

Introduction - flip flops Flip-flops are synchronous bi-stable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, the changes in the output occur in synchronization with the clock.

Necessity Need for active storage devices like RAMs, and synchronization in the operations of sequential digital circuits led to the invention of Flip-Flops.

History of flip-flops The first electronic flip-flop was invented in 1918 by the British physicists William Eccles and F. W. Jordan. It was initially called the Eccles–Jordan trigger circuit and consisted of two active elements (vacuum tubes). The design was used in the 1943 British Colossus codebreaking computer and such circuits and their transistorized versions were common in computers even after the introduction of integrated circuits, though flip-flops made from logic gates are also common now.

TYPICAL NAND GATE USING DIODES & BJTs. Diodes and BJTs are used to form this logic circuit. The adjoining fig. gives the symbol, truth table & schematic circuit of a typical DTL IC NAND gate. It is clear that if one or more of the inputs (A-D) are grounded (0 state), the current through the 2KΩ input resistor will be returned to ground. This eliminates the base drive for output transistor Q, so that it is turned OFF. For this case the output is in 1 state. A unique input condition occurs when all the inputs are high, the current will then flow through the input resistor and the two stand out diodes (D5, D6) into the base of Transistor Q, which turns ON Q, taking it to the saturation, i.e. Output is zero level. Thus the circuit performs the positive NAND function.

NAND GATE USING DIODES & BJTs If any or all of the inputs (A,B,C,D,X) are low (logic 0), the output (y) will be high (logic 1). In a unique condition, if all of the inputs are high (logic 1), the output (y) will be low (logic 0). i.e. Y=0, if and only if A=B=C=D=X=1, In all other logics, Y=1. y

What is a flip flop? In digital circuits, the flip-flop, is a kind of bi-stable multi-vibrator. It is a Sequential Circuit / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems. All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip-flops are defined in this presentation.

What is a latch? Set Output Reset In digital electronics, a latch is an electronic logic circuit that has two inputs and one output. One of the inputs is called the SET input; and the other is called the RESET input. Latch circuits can be either active-high or active-low. The difference is determined by whether the operation of the latch circuit is triggered by HIGH or LOW signals on the inputs. Active-high circuit: Both inputs are normally tied to ground (LOW), and the latch is triggered by a momentary HIGH signal on either of the inputs. Active-low circuit: Both inputs are normally HIGH, and the latch is triggered by a momentary LOW signal on either input.

What is a latch? In an active-high latch, both the SET and RESET inputs are connected to ground. When the SET input goes HIGH, the output also goes HIGH. When the SET input returns to LOW, however, the output remains HIGH. In other words, the latch remembers that the SET input has been activated. If the SET input goes HIGH for even a moment, the output goes HIGH and stays HIGH, even after the SET input returns to LOW. The output returns to LOW only when the RESET input goes HIGH.

What is a latch? On the other hand, in an active-low latch the inputs are normally held at HIGH. When the SET input momentarily goes LOW, the output goes HIGH. The output then stays HIGH until the RESET input momentarily goes LOW.

Clock signal Sequential logic circuits have memory. Output is a function of input and present state. Sequential circuits are synchronized by a periodic “clock” signal. When the clock changes from a LOW state to a HIGH state, this is called the positive-going transition (PGT) or positive edge triggered. When the clock changes from a HIGH state to a LOW state, it is called negative going transition (NGT) or negative edge triggered. Fig . A clock signal consists of periodic logic 1 pulses.

Sr (set-reset) flip-flop:

Sr (set-reset) flip-flop: When clock input is high and both set and reset inputs are high, the SR flip-flop jumps into an invalid state, because Q can never be equal to Q-bar. This is a limitation in SR flip-flop.

D Flip-flop A D flip-flop is nothing but a modification over clocked SR flip-flop. In this flip-flop, one input is complimented to the other input to avoid not-used condition in SR flip-flop.

D Flip-flop Properties of D flip-flop: No worry of condition for S=R=1, because of inversion, it is never possible. Most frequently used flip-flop for data storage, e.g. calculators.

JK Flip-flop

Race-around condition JK Flip-flop Race-around condition Here, in the above circuit, we want to make use of the 'not used’ condition that occur in SR flip-flop, so we used a three input NAND gate instead of two input NAND gate, with one of the inputs as a feedback from the previous output. Characteristic table for JK flip flop: (assume that initially Q=0 and Q’=1) Case 1: Clock=1, J=0, K=0, Q=Q, Q’=Q’ (Memory state) Case 2: Clock=1, J=1, K=0, Q=1, Q’=0 Case 3: Clock=1, J=0, K=1, Q=0, Q’=1 Case 4: Clock=1, J=1, K=1, Q=1,0,1,0,1,… Q’=0,1,0,1,0,… The above condition in Case 3, is called as Racing or race-around.

JK Flip-flop The main difference between a JK flip-flop and an SR flip-flop is that in the JK flip-flop, both inputs can be HIGH. When both the J and K inputs are HIGH, the Q output is toggled, which means that the output alternates between HIGH and LOW. Thereby the invalid condition which occurs in the SR flip-flop is eliminated.

T-flip flop The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. It is useful for constructing binary counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both of its inputs high. Clock T Qn+1 X Qn 1 ¯

Applications of flip flops Some of the most common applications of flip – flops are Counters Registers Frequency Divider circuits Data transfer All these applications make use of the flip – flop’s clocked operation. Almost all of them come under the category of sequential circuits.

Thanks