ECE 111 (Spring 2017) http://cwcserv.ucsd.edu/~billlin/classes/ECE111/index.php Professor Bill Lin Office hours: TBD, 4310 Atkinson Hall Lectures: Section A00: TuTh 9:30-10:50a, MANDE B-210 Section B00: TuTh 11:00a-12:20p, CENTER 216 No regular discussion sections (only schedule if needed) TAs: Qingzi Lan, Kevin Luong, and Ping Yin Office hours: TBD Note: You may get help from any TA during their office hours.

Introduction Goal: Learn Verilog-based chip design In particular, we will be using the Hardware Description Language (HDL) SystemVerilog, which is a “superset” of Verilog: Verilog, IEEE standard (1364) in 1995 SystemVerilog, extended in 2005, current version is IEEE Standard 1800-2012 The name “SystemVerilog” is confusing because it still describes hardware at the same level as “Verilog”, but SystemVerilog adds a number of enhancements and improved syntax. SystemVerilog files have a “.sv” extension so that the compiler knows that the file is in SystemVerilog rather than Verilog.

Software See Software Downloads Page which links to this: http://cwcserv.ucsd.edu/~billlin/classes/ECE111/software.php which links to this: http://dl.altera.com/?edition=lite Quartus Prime Lite Edition Quartus Prime (earlier versions were called Quartus II) ModelSim-Intel FPGA Edition Arria II device support Available for Windows and Linux For Macs, you can use Bootcamp to dual-boot Windows

Software Class website has a tutorial page on Quartus and ModelSim http://cwcserv.ucsd.edu/~billlin/classes/ECE111/Quartus_ModelSim_Tutorial/quartus_modelsim_tutorial.html Intel/Altera also has an online demonstration page on Quartus https://www.altera.com/education/demonstrations/dem-index.html

More Information Recommended textbook Digital Design and Computer Architecture, Second Edition, by David Harris and Sarah Harris We will only be using Chapter 4 of this book, which provides a good overview of SystemVerilog with good examples. Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog Book recommended, but not required. This is NOT a lecture-based class. Class time used to talk about SystemVerilog in the beginning, but mostly about project information for the rest of the quarter.

Projects and Grading Final project will be a processor capable of implementing the MD5, SHA-1 and SHA-2 secure hash algorithms. Final project will be evaluated on 2 criteria: MIN DELAY = number of clock cycles / clock frequency MIN AREA*DELAY = area x delay Before the final project, there will be a number of intermediate projects. All intermediate projects P/NP. Final grade based only on the final project based on MIN-DELAY and MIN-AREA*DELAY results. Projects done in teams of 2 (you have the option of working alone).

Synthesis vs. Simulation Extremely important to understand that SystemVerilog is BOTH a “Synthesis” language and a “Simulation” language Small subset of the language is “synthesizable”, meaning that it can be translated to logic gates and flip-flops. SystemVerilog also includes many features for “simulation” or “verification”, features that have no meaning in hardware! Although SystemVerilog syntactically looks like “C”, it is a Hardware Description Language (HDL), NOT a software programming language Every line of synthesizable SystemVerilog MUST have a direct translation into hardware (logic gates and flip flops). Very important to think of the hardware that each line of SystemVerilog will produce.

SystemVerilog Modules module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Module Abstraction: Slide derived from slides by Harris & Harris from their book

HDL Synthesis SystemVerilog: module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Synthesis: translates into a netlist (i.e., a list of gates and flip-flops, and their wiring connections) * Schematic after some logic optimization Slide derived from slides by Harris & Harris from their book

SystemVerilog Syntax Case sensitive No names that start with numbers Example: reset and Reset are not the same signal. No names that start with numbers Example: 2mux is an invalid name Whitespace ignored Comments: // single line comment /* multiline comment */ Slide derived from slides by Harris & Harris from their book

Structural Modeling - Hierarchy module and3(input logic a, b, c, output logic y); assign y = a & b & c; endmodule module inv(input logic a, assign y = ~a; module nand3(input logic a, b, c logic n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverter Slide derived from slides by Harris & Harris from their book

Bitwise Operators // single line comment /*…*/ multiline comment module gates(input logic [3:0] a, b, output logic [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */ assign y1 = a & b; // AND assign y2 = a | b; // OR assign y3 = a ^ b; // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a | b); // NOR endmodule // single line comment /*…*/ multiline comment Slide derived from slides by Harris & Harris from their book

Reduction Operators module and8(input logic [7:0] a, output logic y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule Slide derived from slides by Harris & Harris from their book

Conditional Assignment module mux2(input logic [3:0] d0, d1, input logic s, output logic [3:0] y); assign y = s ? d1 : d0; endmodule ? : is also called a ternary operator because it operates on 3 inputs: s, d1, and d0. Slide derived from slides by Harris & Harris from their book

Precedence Order of operations ~ NOT *, /, % mult, div, mod +, - Highest ~ NOT *, /, % mult, div, mod +, - add,sub <<, >> shift <<<, >>> arithmetic shift <, <=, >, >= comparison ==, != equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR |, ~| OR, NOR ?: ternary operator Lowest Slide derived from slides by Harris & Harris from their book

Adder Examples module fulladder(input logic a, b, cin, output logic s, cout); logic p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule Slide derived from slides by Harris & Harris from their book

Adder Examples /* hierarchical 4-bit adder */ module h4ba(input logic [3:0] A, B, input logic carry_in, output logic [3:0] sum, output logic carry_out); logic carry_out_0, carry_out_1, carry_out_2; // internal signals fulladder fa0 (A[0], B[0], carry_in, sum[0], carry_out_0); fulladder fa1 (A[1], B[1], carry_out_0, sum[1], carry_out_1); fulladder fa2 (A[2], B[2], carry_out_1, sum[2], carry_out_2); fulladder fa3 (A[3], B[3], carry_out_2, sum[3], carry_out); endmodule each of these is an instantiation of “full_adder”

Adder Examples module add4(input logic [3:0] A, B, output logic [3:0] sum); assign sum = A + B; endmodule Verilog compilers will replace arithmetic operators with default logic implementations (e.g. ripple carry adder) this expands into logic for a ripple carry adder

Numbers Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal) Number # Bits Base Decimal Equivalent Stored 3'b101 3 binary 5 101 'b11 unsized 00…0011 8'b11 8 00000011 8'b1010_1011 171 10101011 3'd6 decimal 6 110 6'o42 octal 34 100010 8'hAB hexadecimal 42 00…0101010 Slide derived from slides by Harris & Harris from their book

Bit Manipulations: Example 1 assign y = {a[2:1], {3{b[0]}}, a[0], 6'b100_010}; // if y is a 12-bit signal, the above statement produces: // y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0 // underscores (_) are used for formatting only to make // it easier to read. SystemVerilog ignores them. Slide derived from slides by Harris & Harris from their book

Bit Manipulations: Example 2 module mux2_8(input logic [7:0] d0, d1, input logic s, output logic [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule Slide derived from slides by Harris & Harris from their book