Data Handling Processor Status/Plans

Slides:

Advertisements

Similar presentations

Georgia Tech Digital Back-end µHRG interface Curtis Mayberry School of Electrical and Computer Engineering Georgia Institute of Technology January 13 th,

Advertisements

Cambridge, Massachusetts Analog Logic Ben Vigoda.

SOI Detector (1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb, Wojciech Kucewicz, Łukasz Mik, Maria Sapor (2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik,

Chip Developments of the Bonn Group Hans Krüger, Bonn University -1-

Capstone Fall 2005 GFX-One Guitar Processor Team Carpal Tunnel October 6 th 2005.

SVT TDR meeting – March 30, 2012 List of peripheral blocks for SVT strip readout chips.

3/7/05A. Semenov Batch-by-Batch Intensity Monitor 1 Two-Channel Batch by Batch Intensity Monitor for Main Injector BBI.

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 9 – Part 1.

Phase-1 Design. i PHC Phase /04/2008 System Overview Clock, JTAG, sync marker and power supply connections Digital output.

Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.

Digital AM Receiver System Hassen Abdu, Ebad Ahmed, Wajahat Khan April 21, Introductory Digital Systems Laboratory.

Verification work Arild Velure. Goals As only part of the final functionality has been implemented for this MPW1, the focus for the testing has.

RD53 Analog IP blocks WG : developments and plans at CPPM M. Barbero, L. Gallin Martel (LPSC), Dzahini (LPSC), D. Fougeron, R. Gaglione (LAPP), F. Gensolen,

Motivation for 65nm CMOS technology

QIE10 development Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear.

2/June/2009LHCb Upgrade1 Single ended ADC Differential ADC –Convert single ended signal to differential (use AD8138 amp) –ASIC differential output ADC.

1 EMCM Measurements Florian Lütticke, Martin Ritter, Felix Müller.

Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution.

DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.

DHPT Architecture & Implementation Tomasz Hemperek Review - MPI

H. Krüger, , DEPFET Workshop, Heidelberg1 System and DHP Development Module overview Data rates DHP function blocks Module layout Ideas & open questions.

Data Handling Processor v0.1 Preliminary Test Results - August 2010 Tomasz Hemperek.

ASIC Review DCD. ASIC Review DCD is implemented in UMC 0.18 um CMOS technology 3.2mm x 5mm DCD-B uses bump bonding on the UMC technology.

13 th International Workshop on DEPFET Detectors and Applications, Ringberg, June 2013, Ivan Peric 1 New DCD Chips Ivan Perić.

DHH progress report Igor Konorov TUM, Physics Department, E18 DEPFET workshop, Bonn February 7-9, 2011 Outline:  Implementation synchronous clock distribution.

1 Test of Electrical Multi-Chip Module for Belle II Pixel Detector DPG-Frühjahrstagung der Teilchenphysik, Wuppertal 2015, T43.1 Belle II Experiment DEPFET.

Tomasz Hemperek, STATUS OF DHPT 1.0 PXD/SVD Workshop 5 th February 2013.

MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.

ASICs1 Drain Current Digitizer Chip (DCD) Status and Future Plans.

1 DCD Gain and Pedestal Spread

Computer Organization and Design

Digital to analog converter [DAC]

Chip Config & Drivers – Required Drivers:

DAQ ACQUISITION FOR THE dE/dX DETECTOR

Status of DHP prototypes

The Data Handling Hybrid

Ivan Perić University of Heidelberg Germany

Digital-to-Analog Analog-to-Digital

A 12-bit low-power ADC for SKIROC

V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris

14-BIT Custom ADC Board Rev. B

Topics SRAM-based FPGA fabrics: Xilinx. Altera..

ECAL Front-end development

Data Handling Processor v0.1 First Test Results

DCD – Measurements and Plans

Florian Lütticke, Carlos Marinas, Norbert Wermes

Iwaki System Readout Board User’s Guide

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

ETD meeting Electronic design for the barrel : Front end chip and TDC

DHH progress report Igor Konorov TUM, Physics Department, E18

Hugo França-Santos - CERN

Meeting at CERN March 2011.

Hans Krüger, University of Bonn

Dr. Rabie A. Ramadan Al-Azhar University Lecture 5

1 Input-Output Organization Computer Organization Computer Architectures Lab Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes.

FMC adapter status Luis Miguel Jara Casas 5/09/2017.

Design of Digital Filter Bank and General Purpose Digital Shaper

Electronics for Physicists

Development of the Data Handling Processor DHP

Vertex 2005 November 7-11, 2005 Chuzenji Lake, Nikko, Japan

Digital-to-Analog Analog-to-Digital

Analog to Digital Converters

Propagation Time Delay

A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS

UK ECAL Hardware Status

Electronics for Physicists

DARE180U Platform Improvements in Release 5.6

Presented by T. Suomijärvi

The QUIET ADC Implementation

Common-Mode Voltage Input common-mode voltage is the most important specification when selecting a direct current sensing solution. It is defined as the.

Presentation transcript:

Data Handling Processor Status/Plans Tomasz Hemperek

6th DEPFET Workshop, Bonn 2011 DHP 0.1 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.1 - Status Working: LVDS Input HSTL like Input Slow control (JTAG) Memories read/write Input readout Patter generator DAC Band Gap Processing (*need DCD) High Speed TX testing To Do: DCD communication and synchronization More Processing Radiation test 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DhpTxTest Chip Design ready: December 2010 - MPW canceled Resubmission: February 2011 - MPW canceled 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.2 - Changes Fixes Input routing signed/unsigned convention PRBS Digital improvements/changes Fix to static pedestal Pedestal during acquisition update – JTAG Improved common mode correction Common mode readback … New combined PLL+Ser+TX New I/O cells Improved DACs/ADC 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.2 - Processing DHP 0.1 DHP 0.2 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.2 - Data Processing 1024 rows buffer for data and for pedestals and offsets 8 bit static pedestal subtraction 2 pass common mode correction (signal rejection) 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.2 - Interface LVDS TX Rail-to-Rail LVDS RX + Custom Area I/O Pads 6th DEPFET Workshop, Bonn 2011 7/02/2011

6th DEPFET Workshop, Bonn 2011 DHP 0.2 – PLL+Ser+TX Integrated PLL, Serializer and CML TX Separate power domain 6th DEPFET Workshop, Bonn 2011 7/02/2011

8-bits DAC redesign DHP 0.1 tests showed that the 8-bits DAC and 10-bits ADC had to be redesigned in order to have a rail-to-rail output. 8-bits DAC has been redesigned (schematic level). New op-amp with Avo=64 dB, PM=88.46º and a rail-to-rail output range. R. Hogervorst, et. al.,”A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries”, JSCC, vol. 29, no. 12, pp. 1505-1513, Dec. 1994.

8-bits DAC redesign Rail to rail 8-bits DAC Dynamic response

6th DEPFET Workshop, Bonn 2011 DHP 0.2 Timetable February March April May Digital Design Verification Implementation Analog Designs Sign-off Want to be ready for May 2011 Submission 6th DEPFET Workshop, Bonn 2011 7/02/2011