Counting Room Electronics for the PANDA MVD Harald Kleines, ZEA-2, Forschungszentrum Jülich

PANDA Micro Vertex Detector Innermost detector closest to interaction point Good spatial and time resolution + energy loss measurement for particle identification 4 barrels and 6 disks with Silicon pixel detectors and Silicon strip detectors Silicon pixel readout: TOPIX ASIC developed by INFN Torino Silicon strip readout: PASTA ASIC under development (INFN Torino, University Giessen, Forschungszentrum Jülich) Concentrator board (service board) with optical transceiver for uplink to counting room: CERN GBT chipset (radiation hardness!) TOPIX directly connected to GBT e-links, PASTA via Module Concentrator Pixel part: 162 GBT links, strip part: 37 GBT links

PANDA DAQ No hardware trigger Free-running system L1 trigger: feature extraction on Compute Nodes (ATCA) L2 trigger: event selection on PC-farm SODA: time distribution and synchronization

4 Lane PCIe (Point-to-Point to MCH) MicroTCA for MVD Concentrators/Buffers MicroTCA Crate 4 Lane PCIe (Point-to-Point to MCH) Clocks, Triggers, Control Signals according to MTCA.4 („uTCA for Physics“) Backplane MCH AMC: CPU AMC: Timing AMC: Con-centrator 1 AMC: Con-Centrator 2 AMC: Con-Centrator n SODA Optional Uplink Uplinks Central input for SODA, local distribution on backplane Local uplinks on concentrator AMCs for high data rate subsystems Option for intermediate test systems: use digitizer AMCs CPU for control system + uplink for low data rate subsystems MVD control system tasks: parameter download, environmental data upload, run control,….

PANDA MVD Readout GBT: Serial optical link MMB (MVD Multiplexing Board) Detector Module Service Board (Concentrator) LVDS GBT Uplink GBT: Serial optical link 3.2 Gb/s (+0,16 Gb/s Slow Control) Line Rate 4.8 Gb/s (Reed-Solomon Encoding) Chipset developed by CERN (only for Detector Side) Counting room side Implementation of the GBT protocol in FPGAs Reference implementation available from CERN for several Altera and Xilinx devices (development finished, no Vivado!)

Iterative Development of Lab Systems for the Readout of FEI3, TOPIX2, TOPIX3 Version 1: Dedicated Readout Controller Board 1 Gbit/s optical Link to PC Implementation of SIS1100 Protocol on Virtex-4 (parallel Interface using SIS1100 OPT) Version 2: Based on the ML605 Implementation of an FMC-Adapter (bigger than FMC due to many connectors) Identical 1 Gbit/s optical Uplink to PC Implementation of SIS1100 Protocol on Virtex-6 Mezzanine SIS1100-OPT New Readout Board SIS1100-CMC FMC Adapter ML605

Version 3 (IKP: André Goerres, Simone Esch,……) Ethernet/UDP implementation for uplink to PC GBT implementation on Virtex-6 for realistic TOPIX4 readout chain ML605 does not support SFP+, oscillator issues => Non matching bit rate Topix3 Testboard GBT Ethernet/UDP ML605

PANDA MVD Multiplexing Board (MMB) (Option) SODA via Backplane FPGA implementation tasks: GBT protocol Uplink protocol: not yet decided most slower subdetectors use HADES TRBnet 10G Ethernet (with UDP) reasonable intermediate choice for test installations Mapping between both SODA PCIe (for control and monitoring tasks)

HGF-AMC: A versatile, powerful module (DESY/KIT) MicroTCA.4 board developed in HGF Portfolio “Detector Technologies” Successor of DESY DAMC02 Flexible Extension by FMCs and RTMs possible Based on Kintex-7 Directly usable as concentrator AMC for PANDA MVD

Kintex-7 FPGA: XC7K325T-2FFG900 28nm technology => low power consumption Also on evaluation board KC705, but price at the moment: ca. 1600€ 16 GTX Transceivers up to 12,5 Gb/s Speed grade 2: 10,3125 Gb/s, sufficient for 10G Ethernet (64b66b encoding) 1 PCIe block (endpoint or root block) with Gen1+2 (Gen3 with Soft IP) 500 user IOs 16Mb Block RAM 840 DSP slices

HGF AMC features 4 GTX lanes to the front panel (SFP+) 4 GTX lanes for PCIe on backplane 1 GTX lane for Gb Ethernet on backplane 4 GTX lanes for point-to-point connections on the backplane Data preprocessing possible?? 4 GB DDR3 SDRAM (SODIMM, up to 8 GB)) FMC socket LPC connector 1 GTX port on LPC connector µRTM-Interface 2 GTX ports multiplexed with 6 LVDS lanes 46 LVDS lanes Hotswap controller

RTM for the HGF-AMC 8 GTP Transceivers up to 6.25 Gb/s Increase of multiplexing level Without RTM: ~70 MMBs, 7 MTCA crates With RTM: ~25 MMBs, ~ 25 RTMs, 3 MTCA crates Based on Artix7 (XC7A200T, ca. 250€) for the mapping to the parallel interface to the HGF-AMC Status: Layout finished, under review

Firmware issues FPGA code from lab systems cannot be reused GBT Protocol Mapping Functions DMA Engine PCIe Endpoint UDP 10G Ethernet GBT Protocol SODA FPGA code from lab systems cannot be reused Mapping function still undefined How much TOPIX specific code? How much support for the control system? DMA engine: commercial core from Northwest Logic? 10G Ethernet /UDP: Free cores available? License for Xilinx IP required? GBT Protocol: Reference implementation available from CERN, only ISE Staff resources: ~0,3 FTE (M. Drochner) Insufficient: further resources have to acquired in ZEA-2 during the year